參數(shù)資料
型號： AK4368EG
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： DAC with built-in PLL & HP-AMP
中文描述： DAC，帶有內(nèi)置的鎖相環(huán)
文件頁數(shù)： 37/60頁
文件大?。?/td> 817K
代理商： AK4368EG
ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 37 -
4) LIN/RIN/MIN
→
Lineout
Power Supply
PDN pin
PMVCM bit
LOUT/ROUT pins
(7)
LMUTE,
ATTS3-0 bits
10H(MUTE)
0FH(0dB)
(Hi-Z)
(Hi-Z)
(7)
(7)
LIN/RIN/MIN pins
(4)
(Hi-Z)
(Hi-Z)
MUTEN bit
Don’t care
(1) >150ns
(2) >0s
PMLO bit
LINL, RINR, MINL, MINR bits
(3) >0s
(5) >0s
3D1-0 bits
(when 3D is used)
(6) >2ms(at 3D OFF), >50ms(at 3D ON)
“00” (3D OFF)
“01”, “10” or “11” (3D ON)
“00”
“01”, “10” or “11”
(6) >2ms or >50ms
Figure 29. Power-up/down sequence of LIN/RIN/MIN and LOUT/ROUT
(1) PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when
DAC is not used.
(2) PMVCM bit should be changed to “1” after PDN pin goes “H”.
(3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”.
(4) When LINL, MINL, RINR or MINR bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.475 x AVDD.
(5) When the 3D function is used, 3D1-0 bits should be changed to “01”, “10” or “11” after LINL, MINL, RINR and
MINR bits are changed to “1”.
(6) When the 3D function is not used, MUTEN and PMLO bits should be changed to “1” at least 2ms (in case external
capacitance at VCOM pin is 2.2
μ
F) after LINL, MINL, RINR and MINR bits are changed to “1”. When the 3D
function is used, MUTEN and PMLO bits should be changed to “1” at least 50ms after 3D1-0 bits are changed to
“01”, “10” or “11”.
(7) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
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