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參數(shù)資料
| 型號： | AK4368EG |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 18/60頁 |
| 文件大小： | 817K |
| 代理商： | AK4368EG |
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ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 18 -
In slave mode, a reference clock of PLL is selected among the input clocks to BICK or LRCK pin. The required clock to
the AK4368 is generated by an internal PLL circuit. BICK and LRCK inputs should be synchronized with MCKO output
(Figure 12).
AK4368
DSP or
μ
P
MCKO
BICK
LRCK
SDATA
BCLK
LRCK
SDTO
MCKI
1fs
32fs ~ 64fs
256fs/128fs/64fs/32fs
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
MCLK
Figure 12. PLL Slave Mode
In slave mode (M/S bit = “0”), the MCKO pin outputs an abnormal frequency clock when the MCKO bit = “1” before the
PLL is locked by setting PMPLL = PMDAC bits = “0”
“1”. After the PLL is locked, the MCKO pin outputs the clock
selected by Table 3. LRCK input should be synchronized with MCKI or MCKO in slave mode. LRCK and BICK should
always be present whenever the AK4368 is in normal operation mode (PMDAC bit = “1”). If these clocks are not
provided, the AK4368 may draw excess current and will not operate properly because it utilizes these clocks for internal
dynamic refresh of registers. If the external clocks are not present, the AK4368 should be placed in power-down mode
(PMDAC bit = “0”).
Mode
PLL3
PLL2
PLL1
PLL0
MCKI
R and C of VCOC pin
R[
]
10k
10k
10k
10k
10k
15k
10k
10k
15k
10k
fs
(Note 26)
44.1, 48
44.1, 48
44.1, 48
44.1, 48
44.1, 48
44.1, 48
44.1, 48
44.1, 48
44.1, 48
44.1, 48
44.0995
48.0007
44.0995
48.0007
44.0995
47.9992
44.0995
47.9997
N/A
C[F]
22n
22n
47n
22n
22n
330n
47n
47n
330n
47n
PLL Lock
Time (typ)
20ms
20ms
20ms
20ms
20ms
100ms
20ms
20ms
100ms
20ms
0
1
2
3
4
5
6
7
8
9
10
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
11.2896MHz
14.4MHz
12MHz
19.2MHz
15.36MHz
13MHz
19.68MHz
19.8MHz
26MHz
27MHz
Default
1
0
1
0
13MHz
10k
22n
20ms
11
1
0
1
1
26MHz
10k
22n
20ms
12
1
1
0
0
19.8MHz
10k
22n
20ms
13
1
1
0
1
27MHz
10k
22n
20ms
14-15
Others
N/A
N/A
N/A
-
Note 26. Type 1-4 frequency is indicated in Table 2.
Table 1. MCKI Input Frequency (PLL mode)
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