參數(shù)資料
型號(hào)： AK4368EG
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： DAC with built-in PLL & HP-AMP
中文描述： DAC，帶有內(nèi)置的鎖相環(huán)
文件頁(yè)數(shù)： 48/60頁(yè)
文件大?。?/td> 817K
代理商： AK4368EG
ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 48 -
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4368. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 0CH prior to generating a stop condition, the address
counter will “roll over” to 00H and the previous data will be overwritten.
The AK4368 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4368 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4368 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledgement to the data but instead generates a stop
condition, the AK4368 ceases transmission.
SDA
Slave
Address
S
S
T
A
R
T
R/W="1"
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
S
T
O
P
Data(n)
Figure 43. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4368 then generates an
acknowledgement, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledgement to the data but instead generates a stop condition, the AK4368 ceases transmission.
SDA
Slave
Address
S
S
T
A
R
T
R/W="0"
A
C
K
A
C
K
A
C
K
Data(n)
A
C
K
Data(n+x)
A
C
K
P
S
T
O
P
Sub
Address(n)
S
Slave
Address
R/W="1"
S
T
A
R
T
Data(n+1)
A
C
K
A
C
K
Figure 44. RANDOM ADDRESS READ
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