參數(shù)資料
型號(hào)： AK4368EG
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： DAC with built-in PLL & HP-AMP
中文描述： DAC，帶有內(nèi)置的鎖相環(huán)
文件頁(yè)數(shù)： 19/60頁(yè)
文件大?。?/td> 817K
代理商： AK4368EG
ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 19 -
fs
Default
Mode
FS3 FS2 FS1 FS0
Type 1
48kHz
24kHz
12kHz
32kHz
16kHz
8kHz
44.1kHz
22.05kHz
11.025kHz
Type 2
48.0007kHz
24.0004kHz
12.0002kHz
32.0005kHz
16.0002kHz
8.0001kHz
44.0995kHz
22.0498kHz
11.0249kHz
Type 3
47.9992kHz
23.9996kHz
11.9998kHz
31.9994kHz
15.9997kHz
7.9999kHz
44.0995kHz
22.0498kHz
11.0249kHz
Type 4
47.9997kHz
23.9999kHz
11.9999kHz
31.9998kHz
15.9999kHz
7.9999kHz
44.0995kHz
22.0498kHz
11.0249kHz
0
1
2
4
5
6
8
9
10
3, 7,
11-15
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
Others
N/A
N/A
N/A
N/A
Table 2. Sampling Frequency (PLL mode)
PS1
0
0
1
1
PS0
0
1
0
1
MCKO
256fs
128fs
64fs
32fs
Default
Table 3. MCKO frequency (PLL mode, MCKO bit = “1”)
Master Mode (M/S bit = “1”)
Power Down
(PMDAC bit= PMPLL bit= “0”)
Input or
fixed to “L” or “H”
Power Up
(PMDAC bit= PMPLL bit= “1”)
Refer to Note 26. Type 1-4
frequency is indicated in Table
2.
Table 1.
MCKO pin MCKO bit = “0”: “L”
MCKO bit = “1”: Output
BICK pin
BF bit = “1”: 64fs output
BF bit = “0”: 32fs output
LRCK pin
Output
PLL Unlock
MCKI pin
Refer to Note 26. Type 1-4
frequency is indicated in
Table 2.
Table 1.
MCKO bit = “0”: “L”
MCKO bit = “1”: Unsettling
“L”
“L”
“L”
“L”
“L”
Table 4. Clock Operation in Master mode (PLL mode)
Slave Mode (M/S bit = “0”)
Power Down
(PMDAC bit= PMPLL bit= “0”)
Input or
fixed to “L” or “H”
Power Up
(PMDAC bit= PMPLL bit= “1”)
Refer to Note 26. Type 1-4
frequency is indicated in Table
2.
Table 1.
MCKO pin MCKO bit = “0”: “L”
MCKO bit = “1”: Output
BICK pin
Input
PLL Unlock
MCKI pin
Refer to Note 26. Type 1-4
frequency is indicated in
Table 2.
Table 1.
MCKO bit = “0”: “L”
MCKO bit = “1”: Unsettling
Input or
Fixed to “L” or “H” externally
Input or
Fixed to “L” or “H” externally
“L”
Fixed to “L” or “H” externally
LRCK pin
Input
Fixed to “L” or “H” externally
Table 5. Clock Operation in Slave mode (PLL mode)
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