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參數(shù)資料
| 型號： | AK4368EG |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 43/60頁 |
| 文件大?。?/td> | 817K |
| 代理商： | AK4368EG |
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ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 43 -
2) DAC
→
Lineout
Power Supply
MCKO pin
BICK, LRCK pins
Don’t care
PDN pin
M/S, PMVCM, PMPLL,
PMDAC, MCKO bits
MCKI pin
(5)
SDTI pin
DAC Internal
State
PD
Normal Operation
PMLO bit
ATTL/R7-0 bits
00H(MUTE)
FFH(0dB)
LOUT/ROUT pins
(9)
LMUTE,
ATTS3-0 bits
10H(MUTE)
0FH(0dB)
(10) GD (11) 1061/fs
(Hi-Z)
PD
Normal Operation
00H(MUTE)
FFH(0dB)
(Hi-Z)
(10)
(11)
(9)
(9)
(10) (11)
Don’t care
Don’t care
(1) >150ns
(2)
>0
(8) >0 (at 3D OFF)
DACL,
DACR bits
(6) >0
3D1-0 bits
(when 3D is used)
(7) >0
“00”(3D OFF)
“01”(3D ON)
“00”
“01”
(8) >0 (at 3D ON)
Unstable
“L”
Don’t care
Unstable
Unstable
(4) ~20ms
(3)
Don’t care
Unstable
Unstable
Unstable
Unstable
(8) >0 (at 3D OFF)
(8) >0 (at 3D ON)
(4) ~20ms
(7) >0
(6) >0
Figure 35. Power-up/down sequence of DAC and LOUT/ROUT(Don’t care: except Hi-Z)
(1) PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM, PMPLL, PMDAC, MCKO and M/S bits should be changed to “1” after PDN pin goes “H”.
(3) The PLL executes when the system clock is input to MCKI.
(4) The PLL lock time is referred to Note 26. Type 1-4 frequency is indicated in Table 2.
(5) Table 1. After the PLL is locked, each clock is output from BICK, LRCK and MCKO pins.
(6) DACL and DACR bits should be changed to “1” after the PLL is locked.
(7) When the 3D function is used, 3D1-0 bits should be changed to “01” after DACL and DACR bits are changed to “1”.
(8) PMLO bit is changed to “1”.
(9) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
(10) Analog output corresponding to the digital input has a group delay (GD) of 22fs(=499
μ
s@fs=44.1kHz).
(11) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
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