參數(shù)資料
型號(hào)： ADSP-21060LCWZ-160
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 48-BIT, 40 MHz, OTHER DSP, CQFP240
封裝： THERMALLY ENHANCED, METRIC, HEAT SINK, CERAMIC, QFP-240
文件頁(yè)數(shù)： 4/48頁(yè)
文件大?。?/td> 481K
代理商： ADSP-21060LCWZ-160
–12–
ADSP-21060C/ADSP-21060LC
REV. B
SYSTEM
CLKIN
EMU
5k
*
TDI
TDO
5k
TDI
EMU
TMS
TCK
TDO
TRST
CLKIN
*OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
*
Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform op-
erations such as starting, stopping and single-stepping multiple
ADSP-21060 in a synchronous manner. If you do not need these
operations to occur synchronously on the multiple processors,
simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and CLKIN
is connected, clock skew between the multiple ADSP-21060C/
ADSP-21060LC processors and the CLKIN pin on the EZ-ICE
header must be minimal. If the skew is too large, synchronous
operations may be off by one or more cycles between proces-
sors. For synchronous multiprocessor operation TCK, TMS,
CLKIN and
EMU should be treated as critical signals in terms
of skew, and should be laid out as short as possible on your
board. If TCK, TMS and CLKIN are driving a large number of
ADSP-21060 (more than eight) in your system, then treat them
as a clock tree using multiple drivers to minimize skew. (See
Figure 7, JTAG Clock Tree, and Clock Distribution in the
High Frequency Design Considerations section of the ADSP-
2106x User’s Manual, Second Edition.)
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO,
EMU, and TRST are not
critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the ADSP-
2100 Family JTAG EZ-ICE User’s Guide and Reference.
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