參數(shù)資料
型號： ADSP-21060LCWZ-160
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： 48-BIT, 40 MHz, OTHER DSP, CQFP240
封裝： THERMALLY ENHANCED, METRIC, HEAT SINK, CERAMIC, QFP-240
文件頁數(shù)： 23/48頁
文件大?。?/td> 481K
代理商： ADSP-21060LCWZ-160
ADSP-21060C/ADSP-21060LC
–3–
REV. B
GENERAL DESCRIPTION
The ADSP-2106x SHARC—Super Harvard Architecture Com-
puter—is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-2106x
SHARCs are 32-bit processors optimized for high performance
DSP applications. The ADSP-2106x builds on the ADSP-
21000 DSP core to form a complete system-on-a-chip, adding a
dual-ported on-chip SRAM and integrated I/O peripherals sup-
ported by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-2106x has a 25 ns instruction cycle time and operates
at 40 MIPS. With its on-chip instruction cache, the processor
can execute every instruction in a single cycle. Table I shows
performance benchmarks for the ADSP-2106x.
The ADSP-2106x SHARC represents a new standard of inte-
gration for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system features
including a 4 Mbit SRAM memory host processor interface,
DMA controller, serial ports, and link port and parallel bus
connectivity for glueless DSP multiprocessing.
Figure 1 shows a block diagram of the ADSP-21060C/
ADSP-21060LC, illustrating the following architectural features:
Computation Units (ALU, Multiplier and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port and Multiprocessor Interface
DMA Controller
Serial Ports and Link Ports
JTAG Test Access Port
Figure 2 shows a typical single-processor system. A multi-
processing system is shown in Figure 3.
Table I. ADSP-21060C/ADSP-21060LC Benchmarks
(@ 40 MHz)
1024-Pt. Complex FFT
0.46 ms
18,221 cycles
(Radix 4, with Digit Reverse)
FIR Filter (per Tap)
25 ns
1 cycle
IIR Filter (per Biquad)
100 ns
4 cycles
Divide (y/x)
150 ns
6 cycles
Inverse Square Root (1/
√x)
225 ns
9 cycles
DMA Transfer Rate
240 Mbytes/s
S
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