參數(shù)資料
型號(hào): ADSP-21060LCWZ-160
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 48-BIT, 40 MHz, OTHER DSP, CQFP240
封裝: THERMALLY ENHANCED, METRIC, HEAT SINK, CERAMIC, QFP-240
文件頁(yè)數(shù): 27/48頁(yè)
文件大?。?/td> 481K
代理商: ADSP-21060LCWZ-160
ADSP-21060C/ADSP-21060LC
–33–
REV. B
Link Ports: 2
CLK Speed Operation
Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can
be introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in
LDATA relative to LCLK, (setup skew = tLCLKTWH min – tDLDCH – tSLDCL). Hold skew is the maximum delay that can be intro-
duced in LCLK relative to LDATA, (hold skew = tLCLKTWL min – tHLDCH – tHLDCL). Calculations made directly from 2
× speed
specifications will result in unrealistically small skew times because they include multiple tester guardbands. The setup and hold skew
times shown below are calculated to include only one tester guardband.
ADSP-21060C Setup Skew
=
0.62 ns max (If port 2 is transmitter, setup skew is 0.39)
ADSP-21060C Hold Skew
=
2.40 ns max
ADSP-21060LC Setup Skew
=
1.23 ns max
ADSP-21060LC Hold Skew
=
2.76 ns max
ADSP-21060C
ADSP-21060LC
Parameter
Min
Max
Min
Max
Unit
Receive
Timing Requirements:
tSLDCL
Data Setup before LCLK Low
2.5
2.25
ns
tHLDCL
Data Hold after LCLK Low
2.25
ns
tLCLKIW
LCLK Period (2
× Operation)
tCK/2
ns
tLCLKRWL
LCLK Width Low
4.5
5.25
ns
tLCLKRWH
LCLK Width High
4.25
4.5
ns
Switching Characteristics:
tDLAHC
LACK High Delay after CLKIN High
18 + DT/2
28.5 + DT/2
18 + DT/2
29.5 + DT/2
ns
tDLALC
LACK Low Delay after LCLK High
1
6
16.5
6
18.5
ns
Transmit
Timing Requirements:
tSLACH
LACK Setup before LCLK High
19
ns
tHLACH
LACK Hold after LCLK High
–6.75
–6.5
ns
Switching Characteristics:
tDLCLK
LCLK Delay after CLKIN
8
ns
tDLDCH
Data Delay after LCLK High
2.5
2.25
ns
tHLDCH
Data Hold after LCLK High
–2.0
ns
tLCLKTWL
LCLK Width Low
(tCK/4) – 1
(tCK/4) + 1.5
(tCK/4) – 0.75 (tCK/4) + 1.5
ns
tLCLKTWH
LCLK Width High
(tCK/4) – 1.5 (tCK/4) + 1
ns
tDLACLK
LCLK Low Delay after LACK High
(tCK/4) + 9
(3 * tCK/4) + 16.5
(tCK/4) + 9
(3 * tCK/4) + 16.5
ns
NOTE
1LACK will go low with t
DLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
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