參數(shù)資料
型號(hào)： ADSP-21060LCWZ-160
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 48-BIT, 40 MHz, OTHER DSP, CQFP240
封裝： THERMALLY ENHANCED, METRIC, HEAT SINK, CERAMIC, QFP-240
文件頁(yè)數(shù)： 15/48頁(yè)
文件大?。?/td> 481K
代理商： ADSP-21060LCWZ-160
–22–
ADSP-21060C/ADSP-21060LC
REV. B
ADSP-21060C
ADSP-21060LC
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tSSDATI
Data Setup before CLKIN
3 + DT/8
ns
tHSDATI
Data Hold after CLKIN
3.5 – DT/8
ns
tDAAK
ACK Delay after Address,
MSx,
SW, BMS1, 2
14 + 7 DT/8 + W
ns
tSACKC
ACK Setup before CLKIN
2
6.5 + DT/4
ns
tHACK
ACK Hold after CLKIN
–1 – DT/4
ns
Switching Characteristics:
tDADRO
Address,
MSx, BMS, SW Delay
after CLKIN
1
7 – DT/8
ns
tHADRO
Address,
MSx, BMS, SW Hold
after CLKIN
–1 – DT/8
ns
tDPGC
PAGE Delay after CLKIN
9 + DT/8
16 + DT/8
9 + DT/8
16 + DT/8
ns
tDRDO
RD High Delay after CLKIN
–2 – DT/8
4 – DT/8
–2 – DT/8
4 – DT/8
ns
tDWRO
WR High Delay after CLKIN
–3 – 3DT/16
4 – 3DT/16
–3 – 3DT/16
4 – 3DT/16
ns
tDRWL
RD/WR Low Delay after CLKIN
8 + DT/4
12.5 + DT/4
8 + DT/4
12.5 + DT/4
ns
tSDDATO Data Delay after CLKIN
19 + 5DT/16
19.25 + 5DT/16
ns
tDATTR
Data Disable after CLKIN
3
0 – DT/8
7 – DT/8
0 – DT/8
7 – DT/8
ns
tDADCCK ADRCLK Delay after CLKIN
4 + DT/8
10 + DT/8
4 + DT/8
10 + DT/8
ns
tADRCK
ADRCLK Period
tCK
ns
tADRCKH ADRCLK Width High
(tCK/2 – 2)
ns
tADRCKL ADRCLK Width Low
(tCK/2 – 2)
ns
W = (number of Wait states specified in WAIT register)
× t
CK.
NOTES
1The falling edge of
MSx, SW, BMS is referenced.
2ACK Delay/Setup: User must meet t
DAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for assertion
of ACK (High).
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
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