參數(shù)資料
型號： ADSP-21060LCWZ-160
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： 48-BIT, 40 MHz, OTHER DSP, CQFP240
封裝： THERMALLY ENHANCED, METRIC, HEAT SINK, CERAMIC, QFP-240
文件頁數(shù)： 20/48頁
文件大?。?/td> 481K
代理商： ADSP-21060LCWZ-160
ADSP-21060C/ADSP-21060LC
–27–
REV. B
ADSP-21060C
ADSP-21060LC
Parameter
Min
Max
Min
Max
Unit
Read Cycle
Timing Requirements:
tSADRDL
Address Setup/
CS Low before RD Low1
00
ns
tHADRDH
Address Hold/
CS Hold Low after RD
00
ns
tWRWH
RD/WR High Width
6
ns
tDRDHRDY
RD High Delay after REDY (O/D) Disable
0
ns
tDRDHRDY
RD High Delay after REDY (A/D) Disable
0
ns
Switching Characteristics:
tSDATRDY
Data Valid before REDY Disable from Low
2
ns
tDRDYRDL
REDY (O/D) or (A/D) Low Delay after
RD Low
10
12.5
ns
tRDYPRD
REDY (O/D) or (A/D) Low Pulsewidth
for Read
45 + 21DT/16
ns
tHDARWH
Data Disable after
RD High
2
8
2
8.5
ns
Write Cycle
Timing Requirements:
tSCSWRL
CS Low Setup before WR Low
0
ns
tHCSWRH
CS Low Hold after WR High
0
ns
tSADWRH
Address Setup before
WR High
5
ns
tHADWRH
Address Hold after
WR High
2
ns
tWWRL
WR Low Width
7
ns
tWRWH
RD/WR High Width
6
ns
tDWRHRDY
WR High Delay after REDY
(O/D) or (A/D) Disable
0
ns
tSDATWH
Data Setup before
WR High
5
ns
tHDATWH
Data Hold after
WR High
1
ns
Switching Characteristics:
tDRDYWRL
REDY (O/D) or (A/D) Low Delay
after
WR/CS Low
10
12.5
ns
tRDYPWR
REDY (O/D) or (A/D) Low Pulsewidth
for Write
15 + 7DT/16
ns
tSRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
1 + 7DT/16
8 + 7DT/16
1 + 7DT/16
8 + 7DT/16
ns
NOTE
1Not required if
RD and address are valid t
HBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD
or
WR goes low or by t
HBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Proces-
sor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Second Edition.
CLKIN
REDY (O/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
tSRDYCK
REDY (A/D)
Figure 18a. Synchronous REDY Timing
Asynchronous Read/Write—Host to ADSP-2106x
Use these specifications for asynchronous host processor accesses
of an ADSP-2106x, after the host has asserted
CS and HBR
(low). After
HBG is returned by the ADSP-2106x, the host can
drive the
RD and WR pins to access the ADSP-2106x’s internal
memory or IOP registers.
HBR and HBG are assumed low for
this timing.
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