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參數(shù)資料
| 型號(hào)： | ADSP-21060LCWZ-160 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 48-BIT, 40 MHz, OTHER DSP, CQFP240 |
| 封裝： | THERMALLY ENHANCED, METRIC, HEAT SINK, CERAMIC, QFP-240 |
| 文件頁(yè)數(shù)： | 13/48頁(yè) |
| 文件大?。?/td> | 481K |
| 代理商： | ADSP-21060LCWZ-160 |
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–20–
ADSP-21060C/ADSP-21060LC
REV. B
ADSP-21060C
ADSP-21060LC
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tDAD
Address, Selects Delay to Data Valid
1, 2
18 + DT + W
ns
tDRLD
RD Low to Data Valid1
12 + 5DT/8 + W
ns
tHDA
Data Hold from Address, Selects
3
0.5
ns
tHDRH
Data Hold from
RD High3
2.0
ns
tDAAK
ACK Delay from Address, Selects
2, 4
14 + 7DT/8 + W
ns
tDSAK
ACK Delay from
RD Low4
8 + DT/2 + W
ns
Switching Characteristics:
tDRHA
Address, Selects Hold after
RD High
0 + H
ns
tDARL
Address, Selects to
RD Low2
2 + 3DT/8
ns
tRW
RD Pulsewidth
12.5 + 5DT/8 + W
ns
tRWR
RD High to WR, RD, DMAGx Low
8 + 3DT/8 + HI
ns
tSADADC Address, Selects Setup before
ADRCLK High
2
0 + DT/4
ns
W = (number of wait states specified in WAIT register)
× t
CK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1Data Delay/Setup: User must meet t
DAD or tDRLD or synchronous spec tSSDATI.
2The falling edge of
MSx, SW, BMS is referenced.
3Data Hold: User must meet t
HDA or tHDRH or synchronous spec tHSDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times
given capacitive and dc loads.
4ACK Delay/Setup: User must meet t
DAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).
WR, DMAG
ACK
DATA
RD
ADDRESS
MSx, SW
BMS
tDARL
tRW
tDAD
tSADADC
tDAAK
tHDRH
tHDA
tRWR
tDRLD
ADRCLK
(OUT)
tDRHA
tDSAK
Figure 13. Memory Read—Bus Master
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is
the bus master accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write – Bus Master below). If
these timing requirements are met, the synchronous read/write
timing can be ignored (and vice versa).
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