參數(shù)資料
型號： ADSP-21060LCWZ-160
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： 48-BIT, 40 MHz, OTHER DSP, CQFP240
封裝： THERMALLY ENHANCED, METRIC, HEAT SINK, CERAMIC, QFP-240
文件頁數(shù)： 14/48頁
文件大?。?/td> 481K
代理商： ADSP-21060LCWZ-160
ADSP-21060C/ADSP-21060LC
–21–
REV. B
ADSP-21060C
ADSP-21060LC
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tDAAK
ACK Delay from Address, Selects
1, 2
14 + 7DT/8 + W
ns
tDSAK
ACK Delay from
WR Low1
8 + DT/2 + W
ns
Switching Characteristics:
tDAWH
Address, Selects to
WR Deasserted2
17 + 15DT/16 + W
ns
tDAWL
Address, Selects to
WR Low2
3 + 3DT/8
ns
tWW
WR Pulsewidth
12 + 9DT/16 + W
ns
tDDWH
Data Setup before
WR High
7 + DT/2 + W
ns
tDWHA
Address Hold after
WR Deasserted
0.5 + DT/16 + H
ns
tDATRWH Data Disable after WR Deasserted
3
1 + DT/16 + H
6 + DT/16 + H
1 + DT/16 + H
6 + DT/16 + H
ns
tWWR
WR High to WR, RD, DMAGx Low
8 + 7DT/16 + H
ns
tDDWR
Data Disable before
WR or RD Low
5 + 3DT/8 + I
ns
tWDE
WR Low to Data Enabled
–1 + DT/16
ns
tSADADC Address, Selects to ADRCLK High
2
0 + DT/4
ns
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is
the bus master accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write–Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
W = (number of wait states specified in WAIT register)
× t
CK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTES
1ACK Delay/Setup: User must meet t
DAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).
2The falling edge of
MSx, SW, BMS is referenced.
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
RD , DMAG
ACK
DATA
WR
ADDRESS
MSx , SW
BMS
tDAWL
tWW
tSADADC
tDAAK
tWWR
tWDE
ADRCLK
(OUT)
tDDWR
tDATRWH
tDWHA
tDDWH
tDAWH
tDSAK
Figure 14. Memory Write—Bus Master
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參數(shù)描述
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