參數資料
型號: ADSP-21060LCWZ-160
廠商: ANALOG DEVICES INC
元件分類: 數字信號處理
英文描述: 48-BIT, 40 MHz, OTHER DSP, CQFP240
封裝: THERMALLY ENHANCED, METRIC, HEAT SINK, CERAMIC, QFP-240
文件頁數: 30/48頁
文件大?。?/td> 481K
代理商: ADSP-21060LCWZ-160
–36–
ADSP-21060C/ADSP-21060LC
REV. B
NOTES
1Referenced to sample edge.
2RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
3Referenced to drive edge.
4Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.
5MCE = 1, TFS enable and TFS valid follow t
DDTLFSE and tDDTENFS.
DT
tDDTTE
tDDTEN
tDDTTI
tDDTIN
DRIVE EDGE
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (INT)
TCLK / RCLK
TCLK (EXT)
CLKIN
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
tDPTR
SPORT DISABLE DELAY
FROM INSTRUCTION
tDCLK
LOW TO HIGH ONLY
TCLK (INT)
RCLK (INT)
TCLK, RCLK
TFS, RFS, DT
CLKIN
TFS (EXT)
tHTFSCK
tSTFSCK
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR
MESH MULTIPROCESSING.
tSDRI
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
tHDRI
tSFSI
tHFSI
tDFSE
tHOFSE
tSCLKIW
DATA RECEIVE– INTERNAL CLOCK
tSDRE
DATA RECEIVE– EXTERNAL CLOCK
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
tHDRE
tSFSE
tHFSE
tDFSE
tSCLKW
tHOFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
tDDTI
tHDTI
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
tSFSI
tHFSI
tSCLKIW
tDFSI
tHOFSI
tDDTE
tHDTE
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
tSFSE
tHFSE
tDFSE
tSCLKW
tHOFSE
DATA TRANSMIT– INTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
Figure 22. Serial Ports
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