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參數(shù)資料
| 型號(hào)： | ADSP-21060LCWZ-160 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 48-BIT, 40 MHz, OTHER DSP, CQFP240 |
| 封裝： | THERMALLY ENHANCED, METRIC, HEAT SINK, CERAMIC, QFP-240 |
| 文件頁(yè)數(shù)： | 24/48頁(yè) |
| 文件大小： | 481K |
| 代理商： | ADSP-21060LCWZ-160 |
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–30–
ADSP-21060C/ADSP-21060LC
REV. B
transfer is controlled by ADDR31-0, RD, WR, MS3-0, and ACK
(not
DMAG). For Paced Master mode, the Memory Read–Bus
Master, Memory Write–Bus Master, and Synchronous Read/
Write–Bus Master timing specifications for ADDR31-0, RD, WR,
MS
3-0, SW, PAGE, DATA47-0, and ACK also apply.
ADSP-21060C
ADSP-21060LC
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tSDRLC
DMARx Low Setup before CLKIN1
55
ns
tSDRHC
DMARx High Setup before CLKIN1
55
ns
tWDR
DMARx Width Low
(Nonsynchronous)
6
ns
tSDATDGL Data Setup after DMAGx Low
2
10 + 5DT/8
ns
tHDATIDG Data Hold after DMAGx High
2
ns
tDATDRH
Data Valid after
DMARx High2
16 + 7DT/8
ns
tDMARLL
DMARx Low Edge to Low Edge
23 + 7DT/8
ns
tDMARH
DMARx Width High
6
ns
Switching Characteristics:
tDDGL
DMAGx Low Delay after CLKIN
9 + DT/4
15 + DT/4
9 + DT/4
15 + DT/4
ns
tWDGH
DMAGx High Width
6 + 3DT/8
ns
tWDGL
DMAGx Low Width
12 + 5DT/8
ns
tHDGC
DMAGx High Delay after CLKIN
–2 – DT/8
6 – DT/8
–2 – DT/8
6 – DT/8
ns
tVDATDGH Data Valid before DMAGx High
3
8 + 9DT/16
ns
tDATRDGH Data Disable after DMAGx High
4
07
0
7
ns
tDGWRL
WR Low before DMAGx Low
0
2
0
2
ns
tDGWRH
DMAGx Low before WR High
10 + 5DT/8 + W
ns
tDGWRR
WR High before DMAGx High
1 + DT/16
3 + DT/16
1 + DT/16
3 + DT/16
ns
tDGRDL
RD Low before DMAGx Low
0
2
0
2
ns
tDRDGH
RD Low before DMAGx High
11 + 9DT/16 + W
ns
tDGRDR
RD High before DMAGx High
0
3
0
3
ns
tDGWR
DMAGx High to WR, RD, DMAGx
Low
5 + 3DT/8 + HI
ns
tDADGH
Address/Select Valid to
DMAGx High 17 + DT
17 + DT
ns
tDDGHA
Address/Select Hold after
DMAGx
High
–0.5
ns
W = (number of wait states specified in WAIT register)
× t
CK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1Only required for recognition in the current cycle.
2t
SDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven tDATDRH after DMARx is brought high.
3t
VDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t VDATDGH = 8 + 9DT/16 + (n
× tCK) where
n equals the number of extra cycles that the access is prolonged.
4See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR31-0, RD, WR, SW, PAGE, MS3-0,
ACK, and
DMAG signals. For Paced Master mode, the data
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