參數(shù)資料
型號(hào): ADSP-21060LCWZ-160
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 48-BIT, 40 MHz, OTHER DSP, CQFP240
封裝: THERMALLY ENHANCED, METRIC, HEAT SINK, CERAMIC, QFP-240
文件頁(yè)數(shù): 10/48頁(yè)
文件大?。?/td> 481K
代理商: ADSP-21060LCWZ-160
–18–
ADSP-21060C/ADSP-21060LC
REV. B
ADSP-21060C
ADSP-21060LC
40 MHz
33 MHz
40 MHz
33 MHz
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Clock Input
Timing Requirements:
tCK
CLKIN Period
25
100
30
100
25
100
30
100
ns
tCKL
CLKIN Width Low
7
9.5
ns
tCKH
CLKIN Width High
5555
ns
tCKRF
CLKIN Rise/Fall (0.4 V–2.0 V)
3
ns
CLKIN
tCKH
tCK
tCKL
Figure 8. Clock Input
ADSP-21060C
ADSP-21060LC
Parameter
Min
Max
Min
Max
Unit
Reset
Timing Requirements:
tWRST
RESET Pulsewidth Low1
4tCK
ns
tSRST
RESET Setup before CLKIN High2
14 + DT/2
tCK
14 + DT/2
tCK
ns
NOTES
1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET
is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.
CLKIN
RESET
tWRST
tSRST
Figure 9. Reset
ADSP-21060C
ADSP-21060LC
Parameter
Min
Max
Min
Max
Unit
Interrupts
Timing Requirements:
tSIR
IRQ2-0 Setup before CLKIN High1
18 + 3DT/4
ns
tHIR
IRQ2-0 Hold before CLKIN High1
12 + 3DT/4
ns
tIPW
IRQ2-0 Pulsewidth2
2 + tCK
ns
NOTES
1Only required for
IRQx recognition in the following cycle.
2Applies only if t
SIR and tHIR requirements are not met.
CLKIN
IRQ2-0
tIPW
tSIR
tHIR
Figure 10. Interrupts
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