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參數(shù)資料
| 型號(hào)： | 7560 |
| 英文描述： | 7560 Group Datasheet Datasheet 1682K/JAN.14.03 |
| 中文描述： | 7560組數(shù)據(jù)表數(shù)據(jù)表1682K/JAN.14.03 |
| 文件頁(yè)數(shù)： | 84/90頁(yè) |
| 文件大小： | 1682K |
| 代理商： | 7560 |
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83
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
SWITCHING CHARACTERISTICS (Extended operating temperature version)
Table 54 Switching characteristics 1 (Extended operating temperature version)
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, Ta = –40 to 85°C, unless otherwise noted)
Notes1:
When the P4
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is “0”.
2:
X
OUT
and X
COUT
pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
(Note 1)
Serial I/O1 output valid time
(Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time
(Note 2)
CMOS output falling time
(Note 2)
140
30
30
0.2
t
C
(S
CLK2
)
40
30
30
Symbol
Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
C
(S
CLK1
)/2–30
t
C
(S
CLK1
)/2–30
–30
10
10
Typ.
Max.
t
wH(S
CLK1
)
t
wL(S
CLK1
)
t
d(S
CLK1
–T
X
D)
t
v(S
CLK1
–T
X
D)
t
r(S
CLK1
)
t
f(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK2
)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
t
f(S
CLK2
)
t
r(CMOS)
t
f(CMOS)
Table 55 Switching characteristics 2 (Extended operating temperature version)
(V
CC
= 2.5 to 4.0 V, V
SS =
0 V, Ta = –20 to 85°C, and V
CC
= 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Notes1:
When the P4
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is “0”.
2:
X
OUT
and X
COUT
pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
(Note 1)
Serial I/O1 output valid time
(Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time
(Note 2)
CMOS output falling time
(Note 2)
350
50
50
0.2
t
C
(S
CLK2
)
50
50
50
Symbol
Parameter
Limits
Min.
t
C
(S
CLK1
)/2–50
t
C
(S
CLK1
)/2–50
–30
20
20
Max.
t
wH(S
CLK1
)
twL(S
CLK1
)
t
d(S
CLK1
–T
X
D)
t
v(S
CLK1
–T
X
D)
t
r(S
CLK1
)
t
f(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK2
)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
t
f(S
CLK2
)
t
r(CMOS)
t
f(CMOS)
Typ.
t
C
(S
CLK2
)/2–160
t
C
(S
CLK2
)/2–160
0
t
C
(S
CLK2
)/2–240
t
C
(S
CLK2
)/2–240
0
Fig. 69 Circuit for measuring output switching characteristics
Measurement output pin
1
0
0
p
F
C
M
O
S
o
u
t
p
u
t
N
o
t
e
:
W
r
d
h
g
r
a
e
i
i
n
s
n
e
o
P
r
7
1
–
(
a
u
t
p
P
d
t
7
7
,
r
e
m
P
s
d
4
0
0
e
)
a
1
n
B
1
d
b
i
t
i
s
4
“
o
1
f
”
t
(
h
N
e
c
U
h
A
a
R
n
T
n
c
l
o
o
n
p
t
e
r
o
n
l
-
e
t
d
u
s
o
0
.
6
)
-
e
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
(
N
o
t
e
)
1 k
1
0
0
p
F
Measurement output pin
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