參數(shù)資料
型號(hào)： 7560
英文描述： 7560 Group Datasheet Datasheet 1682K/JAN.14.03
中文描述： 7560組數(shù)據(jù)表數(shù)據(jù)表1682K/JAN.14.03
文件頁數(shù)： 70/90頁
文件大小： 1682K
代理商： 7560
69
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
Table 28 Switching characteristics 1 (V
CC
= 4.0 to 5.5 V, V
SS =
0 V, Ta = –20 to 85°C, unless otherwise noted)
Notes1:
When the P4
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is “0”.
2:
X
OUT
and X
COUT
pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
(Note 1)
Serial I/O1 output valid time
(Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time
(Note 2)
CMOS output falling time
(Note 2)
140
30
30
0.2
t
C
(S
CLK2
)
40
30
30
Symbol
Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
C
(S
CLK1
)/2–30
t
C
(S
CLK1
)/2–30
–30
10
10
Typ.
Max.
t
wH(S
CLK1
)
t
wL(S
CLK1
)
t
d(S
CLK1
–T
X
D)
t
v(S
CLK1
–T
X
D)
t
r(S
CLK1
)
t
f(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK2
)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
t
f(S
CLK2
)
t
r(CMOS)
t
f(CMOS)
Table 29 Switching characteristics 2 (V
CC
= 2.2 to 4.0 V, V
SS =
0 V, Ta = –20 to 85°C, unless otherwise noted)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Notes1:
When the P4
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is “0”.
2:
X
OUT
and X
COUT
pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
(Note 1)
Serial I/O1 output valid time
(Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time
(Note 2)
CMOS output falling time
(Note 2)
350
50
50
0.2
t
C
(S
CLK2
)
50
50
50
Symbol
Parameter
Limits
Min.
t
C
(S
CLK1
)/2–50
t
C
(S
CLK1
)/2–50
–30
20
20
Max.
t
wH(S
CLK1
)
twL(S
CLK1
)
t
d(S
CLK1
–T
X
D)
t
v(S
CLK1
–T
X
D)
t
r(S
CLK1
)
t
f(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK2
)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK2
–S
OUT2
)
t
f(S
CLK2
)
t
r(CMOS)
t
f(CMOS)
Typ.
t
C
(S
CLK2
)/2–160
t
C
(S
CLK2
)/2–160
0
t
C
(S
CLK2
)/2–240
t
C
(S
CLK2
)/2–240
0
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