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參數(shù)資料
| 型號： | 7560 |
| 英文描述： | 7560 Group Datasheet Datasheet 1682K/JAN.14.03 |
| 中文描述： | 7560組數(shù)據(jù)表數(shù)據(jù)表1682K/JAN.14.03 |
| 文件頁數(shù)： | 26/90頁 |
| 文件大小： | 1682K |
| 代理商： | 7560 |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
25
Fig. 20 Interrupt control
Fig. 21 Structure of interrupt-related registers
I
Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
When switching external interrupt active edge
Related register: Interrupt edge selection register (address 3A
16
)
Timer X mode register (address 27
16
)
Timer Y mode register (address 28
16
)
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection bit of A-D control reg-
ister (bit 6 of address 34
16
)
When not requiring for the interrupt occurrence synchronous with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit (polarity switch bit) or the inter-
rupt source selection bit.
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
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2
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
Timer 1 interrupt request bit
INT
2
interrupt request bit
Serial I/O2 interrupt request bit
Key input interrupt request bit
ADT/AD conversion interrupt request bit
Not used (
“
0
”
at reading)
:
D
1
Interrupt control register 2
(ICON2 : address 003F
16
)
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
Timer 1 interrupt enable bit
INT
2
interrupt enable bit
Serial I/O2 interrupt enable bit
Key input interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (
“
0
”
at reading)
(Write
“
0
”
to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
0 : Falling edge active
1 : Rising edge active
b
7
b
0
b
7
b
0
b7
b0
b
0
7
b0
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相關代理商/技術參數(shù) |
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