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參數(shù)資料
| 型號： | 7560 |
| 英文描述： | 7560 Group Datasheet Datasheet 1682K/JAN.14.03 |
| 中文描述： | 7560組數(shù)據(jù)表數(shù)據(jù)表1682K/JAN.14.03 |
| 文件頁數(shù)： | 36/90頁 |
| 文件大?。?/td> | 1682K |
| 代理商： | 7560 |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
35
Fig. 32 Structure of serial I/O1 control registers
BRG count source selection bit (CSS)
0: f(X
IN
)
1: f(X
IN
)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
External clock input divided by 16 when UART is selected.
S
RDY1
output enable bit (SRDY)
0: P4
7
pin operates as ordinary I/O pin
1: P4
7
pin operates as S
RDY1
output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P4
4
–
P4
7
operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P4
4
–
P4
7
operate as serial I/O pins)
Serial I/O1 control register
(SIO1CON : address 001A
16
)
b7
b0
T
0
1
r
a
B
:
B
n
s
m
f
f
u
f
i
r
r
t
b
f
u
e
u
l
m
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
B
E
)
:
u
e
e
l
f
p
t
y
R
0
1
e
:
:
c
B
B
e
u
u
i
f
f
v
f
f
e
e
e
b
e
r
u
m
u
f
f
e
p
r
t
f
u
l
l
f
l
a
g
(
R
B
F
)
r
y
f
l
l
T
0
1
r
:
:
a
T
T
n
r
r
s
a
a
m
n
n
i
t
m
s
m
s
h
i
t
i
t
i
s
s
f
t
h
h
r
i
i
e
f
t
f
t
g
i
c
i
n
s
t
p
m
e
r
o
p
s
g
l
e
h
r
t
i
f
t
s
d
c
o
m
p
l
e
t
i
o
n
f
l
a
g
(
T
S
C
)
s
r
e
e
s
o
O
0
1
v
:
:
e
N
O
r
o
v
r
u
e
e
n
r
r
r
u
e
o
r
r
r
o
r
f
l
a
g
(
O
E
)
r
n
e
r
r
o
r
P
0
1
a
:
:
r
N
P
i
t
o
a
y
e
r
i
e
r
r
r
o
o
e
r
f
l
a
g
(
P
E
)
r
y
r
r
t
r
o
r
F
0
1
r
:
:
a
N
F
m
o
r
i
n
e
m
g
r
r
i
n
e
o
r
r
r
o
r
f
l
a
g
(
F
E
)
a
g
e
r
r
o
r
S
0
1
u
:
:
m
(
O
(
O
m
E
E
i
)
)
n
g
U
U
e
(
(
r
r
E
E
o
r
)
)
f
U
U
l
a
g
(
F
(
F
(
E
E
S
)
)
E
=
=
)
0
1
P
P
N
o
t
u
s
e
d
(
“
1
”
a
t
r
e
a
d
i
n
g
)
S
(
S
e
r
O
i
a
l
S
I
/
O
T
1
:
s
t
a
a
d
t
u
d
s
r
r
s
e
s
g
i
s
0
t
e
1
r
9
1
I
1
S
e
0
6
)
b7
b0
U
(
U
A
R
A
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
T
c
C
o
n
t
N
r
o
l
a
r
e
d
g
d
i
r
s
e
t
e
s
r
s
R
T
O
:
0
0
1
B
1
6
)
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P4
5
/T
X
D P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (
“
1
”
at reading)
b7
b0
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