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參數(shù)資料
| 型號： | 7560 |
| 英文描述： | 7560 Group Datasheet Datasheet 1682K/JAN.14.03 |
| 中文描述： | 7560組數(shù)據(jù)表數(shù)據(jù)表1682K/JAN.14.03 |
| 文件頁數(shù)： | 41/90頁 |
| 文件大?。?/td> | 1682K |
| 代理商： | 7560 |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
40
A-D CONVERTER
[A-D Conversion Low-Order Register (ADL)]
0014
16
[A-D Conversion High-Order Register (ADH)]
0035
16
The A-D conversion registers are read-only registers that store the
result of an A-D conversion . When reading this register during an
A-D conversion, the previous conversion result is read.
The high-order 8 bits of a conversion result is stored in the A-D
conversion high-order register (address 0035
16
), and the low-or-
der 2 bits of the same result are stored in bit 7 and bit 6 of the A-D
conversion low-order register (address 0014
16
).
Bit 0 of the A-D conversion low-order register is the conversion
mode selection bit. When this bit is set to
“
0
”
, that becomes the
10-bit A-D mode. When this bit is set to
“
1
”
, that becomes the 8-bit
A-D mode.
[A-D Control Register (ADCON)] 0034
16
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 indi-
cates the completion of an A-D conversion. The value of this bit re-
mains at
“
0
”
during an A-D conversion, then it is set to
“
1
”
when
the A-D conversion is completed. Writing
“
0
”
to this bit starts the
A-D conversion.
Bit 4 is the V
REF
input switch bit which controls connection of the
resistor ladder and the reference voltage input pin (V
REF
). The
resistor ladder is always connected to V
REF
when bit 4 is set to
“
1
”
. When bit 4 is set to
“
0
”
, the resistor ladder is cut off from V
REF
except for A-D conversion performed. When bit 5, which is the AD
external trigger valid bit, is set to
“
1
”
, A-D conversion starts also by
a falling edge of an ADT input. When using an A-D external trigger,
set the P5
7
/ADT pin to input mode (set
“
0
”
to bit 7 of port P5 direc-
tion register).
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
by 256 (when 8-bit A-D mode) or 1024 (when 10-
bit A-D mode), and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P6
7
/AN
7
–
P6
0
/AN
0
.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
converter interrupt request bit to
“
1
”
.
Note that because the comparator consists of a capacitor
coupling, set f(X
IN
) to 500 kHz or more during an A-D conversion.
Use the clock divided from the main clock f(X
IN
) as the system clock
φ
.
Fig. 40 Structure of A-D converter-related registers
A
(
A
-
D
D
C
Analog input pin selection bits
b2b1b0
0 0 0 : P6
0
/AN
0
0 0 1 : P6
1
/AN
1
0 1 0 : P6
2
/AN
2
0 1 1 : P6
3
/AN
3
1 0 0 : P6
4
/AN
4
1 0 1 : P6
5
/AN
5
1 1 0 : P6
6
/AN
6
1 1 1 : P6
7
/AN
7
c
o
O
n
N
t
r
o
:
l
a
r
d
e
g
r
i
e
s
t
e
s
r
d
s
0
0
3
4
1
6
)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
V
R
E
i
n
p
u
t
s
w
i
t
0
:
A
U
T
O
1
:
O
N
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
1 : Interrupt request at ADT
input falling
Not used (
“
0
”
at reading)
F
c
h
b
i
t
b7
b0
A
(
A
-
D
D
L
c
o
:
Conversion mode selection bit
0 : 10-bit A-D mode
1 : 8-bit A-D mode
n
a
v
d
e
d
r
r
s
e
i
o
s
n
s
l
o
0
w
1
-
4
1
o
r
6
)
d
e
r
r
e
g
i
s
t
e
r
0
Not used (
“
0
”
at reading)
For
10-bit A-D mode
A-D conversion result
For
8-bit A-D mode
Not used (undefined at reading)
b7
b0
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