參數(shù)資料
型號(hào)： 7560
英文描述： 7560 Group Datasheet Datasheet 1682K/JAN.14.03
中文描述： 7560組數(shù)據(jù)表數(shù)據(jù)表1682K/JAN.14.03
文件頁(yè)數(shù)： 83/90頁(yè)
文件大小： 1682K
代理商： 7560
82
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7560 Group
MITSUBISHI MICROCOMPUTERS
TIMING REQUIREMENTS (Extended operating temperature version)
Table 52 Timing requirements 1 (Extended operating temperature version)
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, Ta = –40 to 85°C, unless otherwise noted)
2
125
45
40
250
105
105
80
80
800
370
370
220
100
1000
400
400
200
200
Note:
When bit 6 of address 001A
16
is “1”.
Divide this value by four when bit 6 of address 001A
16
is “0”.
Reset input “L” pulse width
Main clock input cycle time (X
IN
input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
to INT
2
input “H” pulse width
INT
0
to INT
2
input “L” pulse width
Serial I/O1 clock input cycle time
(Note)
Serial I/O1 clock input “H” pulse width
(Note)
Serial I/O1 clock input “L” pulse width
(Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
(Note)
Serial I/O2 clock input “H” pulse width
(Note)
Serial I/O2 clock input “L” pulse width
(Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
t
w(RESET)
t
c(X
IN
)
t
wH(X
IN
)
t
wL(X
IN
)
t
c(CNTR)
t
wH(CNTR)
t
wL(CNTR)
t
wH(INT)
t
wL(INT)
t
c(S
CLK1
)
t
wH(S
CLK1
)
t
wL(S
CLK1
)
t
su(R
X
D–S
CLK1
)
t
h(S
CLK1
–R
X
D)
t
c(S
CLK2
)
t
wH(S
CLK2
)
t
wL
(S
CLK2
)
t
su(S
IN2
–S
CLK2
)
t
h(S
CLK2
–S
IN2
)
Symbol
Parameter
Limits
Typ.
Min.
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Max.
Table 53 Timing requirements 2 (Extended operating temperature version)
(V
CC
= 2.5 to 4.0 V, V
SS =
0 V, Ta = –20 to 85°C, and V
CC
= 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted)
2
125
45
40
500/(V
CC
-2)
250/(V
CC
-2)–20
250/(V
CC
-2)–20
230
230
2000
950
950
400
200
2000
950
950
400
300
Reset input “L” pulse width
Main clock input cycle time (X
IN
input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
to INT
2
input “H” pulse width
INT
0
to INT
2
input “L” pulse width
Serial I/O1 clock input cycle time
(Note)
Serial I/O1 clock input “H” pulse width
(Note)
Serial I/O1 clock input “L” pulse width
(Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
(Note)
Serial I/O2 clock input “H” pulse width
(Note)
Serial I/O2 clock input “L” pulse width
(Note)
Serial I/O2 input set up time
Serial I/O2 input hold time
t
w(RESET)
t
c(X
IN
)
t
wH(X
IN
)
t
wL(X
IN
)
t
c(CNTR)
t
wH(CNTR)
t
wL(CNTR)
t
wH(INT)
t
wL(INT)
t
c(S
CLK1
)
t
wH(S
CLK1
)
t
wL(S
CLK1
)
t
su(R
X
D–S
CLK1
)
t
h(S
CLK1
–R
X
D)
t
c(S
CLK2
)
t
wH(S
CLK2
)
t
wL(S
CLK2
)
Symbol
Parameter
Limits
Min.
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ.
Max.
Note:
When bit 6 of address 001A
16
is “1”.
Divide this value by four when bit 6 of address 001A
16
is “0”.
t
su(S
IN2
–S
CLK2
)
t
h(S
CLK2
–S
IN2
)
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