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參數(shù)資料
| 型號： | 7560 |
| 英文描述： | 7560 Group Datasheet Datasheet 1682K/JAN.14.03 |
| 中文描述： | 7560組數(shù)據(jù)表數(shù)據(jù)表1682K/JAN.14.03 |
| 文件頁數(shù)： | 31/90頁 |
| 文件大小： | 1682K |
| 代理商： | 7560 |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
30
Timer Y
Timer Y is a 16-bit timer and is equipped with the timer latch. The
division ratio of timer Y is given by 1/(n+1), where n is the value in
the timer latch. Timer Y is a down-counter. When the contents of
timer Y reach
“
0000
16
”
, an underflow occurs at the next count
pulse and the contents of the timer latch are reloaded into the
timer and the count is continued. When the timer underflows, the
timer Y interrupt request bit is set to
“
1
”
.
Timer Y can be selected in one of four modes by the timer Y mode
register.
(1) Timer mode
The timer counts f(X
IN
)/16 (or f(X
CIN
)/16 in low-speed mode).
(2) Period measurement mode
CNTR
1
interrupt request is generated at rising or falling edge of
CNTR
1
pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down.
Except for this, the operation in period measurement mode is the
same as in timer mode.
The timer value just before the reloading at rising or falling of
CNTR
1
pin input signal is retained until the next valid edge is
input.
The rising or falling timing of CNTR
1
pin input signal can be
discriminated by CNTR
1
interrupt. When using a timer in this
mode, set the P5
5
/CNTR
1
pin to input mode (set
“
0
”
to bit 5 of port
P5 direction register).
(3) Event counter mode
The timer counts signals input through the CNTR
1
pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the
P5
5
/CNTR
1
pin to input mode (set
“
0
”
to bit 5 of port P5 direction
register).
(4) Pulse width HL continuously measure-
ment mode
CNTR
1
interrupt request is generated at both rising and falling
edges of CNTR
1
pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the P5
5
/CNTR
1
pin to input mode (set
“
0
”
to bit 5 of port P5
direction register).
I
Note on CNTR
1
interrupt active edge selection
CNTR
1
interrupt active edge depends on the value of the CNTR
1
active edge switch bit. However, in pulse width HL continuously
measurement mode, CNTR
1
interrupt request is generated at both
rising and falling edges of CNTR
1
pin input signal regardless of
the value of CNTR
1
active edge switch bit.
Fig. 26 Structure of timer Y mode register
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:
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