參數(shù)資料
型號： 7560
英文描述： 7560 Group Datasheet Datasheet 1682K/JAN.14.03
中文描述： 7560組數(shù)據(jù)表數(shù)據(jù)表1682K/JAN.14.03
文件頁數(shù)： 29/90頁
文件大?。?/td> 1682K
代理商： 7560
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
28
TIMERS
The 7560 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0”, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Fig. 24 Timer block diagram
“
1
”
P5
5
/CNTR
1
“
0
”
“
1
0
”
“
00
”
,
“
01
”
,
“
11
”
P5
4
/CNTR
0
Q
Q
T
S
“
0
”
“
1
”
“
0
”
Q
D
“
0
”
l
Q
D
“
1
”
“
0
”
“
1
”
“
1
0
”
Q
T
S
“
0
”
“
1
”
“
0
”
“
1
”
“
1
”
P4
3
/
φ
/T
OUT
X
C
I
N
“
0
”
“
1
”
CNTR
active
edge switch bit
T
s
i
m
e
l
e
c
r
t
i
1
o
n
c
o
b
u
i
t
n
t
s
o
u
r
c
e
e
Real time port
control bit
“
0
”
f(
w
(
I
f
(
h
N
)
/
N
)
φ
1
6
/
=
X
C
e
I
1
6
X
C
n
I
N
/
2
)
C
e
N
d
T
e
R
1
s
a
i
c
t
c
t
i
v
e
b
g
w
h
i
t
Timer Y stop
control bit
i
m
e
Falling edge detection
P
m
e
r
i
o
s
d
u
e
a
r
e
m
e
n
t
m
o
d
e
Timer Y
interrupt
request
P
m
n
u
l
s
a
e
s
u
w
r
i
d
m
t
h
e
H
n
L
t
c
o
o
n
d
t
i
n
u
o
u
s
l
y
e
e
m
e
R
i
s
i
n
g
e
d
g
e
d
e
t
e
c
t
i
o
Timer Y
operating
mode bits
Timer X
interrupt
request
T
w
i
m
r
i
e
e
r
X
i
g
m
n
o
l
d
e
r
e
g
i
s
t
e
r
t
s
a
P
r
e
4
3
g
d
t
i
e
r
e
r
c
t
i
o
n
i
s
Pulse output mode
P
5
4
l
a
t
c
h
Timer X stop
control bit
Timer X write
control bit
L
a
t
c
h
T
i
n
“
0
i
m
g
0
e
m
”
,
r
o
0
X
d
1
e
”
o
p
b
,
“
e
i
t
1
r
s
”
a
t
-
“
1
Pulse width
measurement
mode
C
e
N
d
T
e
R
0
s
a
i
c
t
c
t
i
v
e
b
g
w
h
i
t
Pulse output mode
P5
4
direction register
T
output
active edge
switch bit
“
0
”
T
c
i
m
o
n
e
t
r
r
o
2
l
b
w
i
r
i
t
e
t
Timer 3 count
source selection bit
Timer 2
interrupt
request
Timer 3
interrupt
request
T
s
i
m
e
l
e
c
r
t
i
2
o
n
c
o
b
u
i
t
n
t
s
o
u
r
c
e
e
T
i
n
r
e
i
m
t
e
q
e
r
u
r
u
e
1
p
s
r
t
t
D
a
t
a
b
u
s
R
c
e
o
a
n
l
r
t
o
i
m
l
e
i
p
o
“
1
r
t
t
b
t
”
R
c
e
o
a
n
l
r
t
o
i
m
l
i
p
o
“
1
r
t
t
b
t
”
T
i
m
e
r
3
l
a
t
c
h
(
8
)
T
i
m
e
r
3
r
e
g
i
s
t
e
r
(
8
)
Timer 1 latch (8)
Timer 1 register (8)
Timer 2 latch (8)
T
i
m
e
r
2
r
e
g
i
s
t
e
r
(
8
)
Timer X low-order register (8)
Timer X (low) latch (8)
Timer X (high) latch (8)
T
r
Y
(
l
o
w
)
l
a
t
c
h
(
8
)
T
i
m
e
r
Y
(
h
i
g
h
)
l
a
t
c
h
(
8
)
Latch
P
4
3
l
a
t
c
h
f(X
IN
)/16
(f(X
CIN
)/16 when
φ
= X
CIN
/2)
f(X
IN
)/16
(f(X
CIN
)/16 when
φ
= X
CIN
/2)
f(X
IN
)/16
(f(X
CIN
)/16 when
φ
= X
CIN
/2)
f(X
IN
)/16
(f(X
CIN
)/16 when
φ
= X
CIN
/2)
P
5
2
/
R
T
P
0
P
5
3
/
R
T
P
1
RTP
0
data for
real time port
RTP
data for
real time port
P
5
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
e
2
l
a
t
c
h
P5
3
direction register
P
5
3
a
t
c
h
φ
Timer X high-order register (8)
Timer Y low-order register (8)
T
i
m
e
r
Y
h
i
g
h
-
o
r
d
e
r
r
e
g
i
s
t
e
r
(
8
)
Q
T
O
o
u
s
e
U
t
p
l
e
T
/
φ
u
t
c
t
o
i
n
b
i
t
T
O
o
u
e
n
U
t
p
a
T
/
φ
u
t
b
l
e
b
i
t
T
O
enable bit
U
T
/
φ
output
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