參數(shù)資料
型號: 7560
英文描述: 7560 Group Datasheet Datasheet 1682K/JAN.14.03
中文描述: 7560組數(shù)據(jù)表數(shù)據(jù)表1682K/JAN.14.03
文件頁數(shù): 82/90頁
文件大?。?/td> 1682K
代理商: 7560
81
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
A-D CONVERTER CHARACTERISTICS (Extended operating temperature version)
Table 49 A-D converter characteristics (Extended operating temperature version)
(V
CC
= 3.0 to 5.5 V, V
SS
= AV
SS
= 0 V, Ta = –40 to 85°C, f(X
IN
) = 500 kHz to 8 MHz, in middle/high-speed mode unless otherwise noted)
8-bit A-D mode (when conversion mode selection bit (bit 0 of address 0014
16
) is “1”)
Symbol
Parameter
Limits
Typ.
Min.
Unit
Max.
8
±2
Test conditions
Resolution
Absolute accuracy
(excluding quantization error)
V
CC
= V
REF
= 3.0 to 5.5 V
Bits
LSB
35
150
tc(ADCLK)
(Note)
k
μ
A
μ
A
Conversion time
Ladder resistor
Reference power source input current
Analog port input current
t
CONV
R
LADDER
I
VREF
I
IA
D-A CONVERTER CHARACTERISTICS (Extended operating temperature version)
Table 51 D-A converter characteristics (Extended operating temperature version)
(V
CC
= 3.0 to 5.5 V, V
CC
= V
REF
, V
SS
= AV
SS
= 0 V, Ta = –40 to 85°C, in middle/high-speed mode unless otherwise noted)
Symbol
Parameter
Limits
Typ.
Min.
Unit
Max.
8
1.0
2.0
Test conditions
Resolution
V
CC
= V
REF
= 5 V
V
CC
= V
REF
= 3.0 V
1
Bits
%
%
μ
s
k
mA
3
2.5
Note:
Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “00
16
”, and excluding currents flowing through
the A-D resistance ladder.
(Note)
Setting time
Output resistor
Reference power source input current
t
su
R
O
I
VREF
4
3.2
12
50
Absolute accuracy
100
200
5.0
V
REF
= 5 V
Table 50 A-D converter characteristics (Extended operating temperature version)
(V
CC
= 3.0 to 5.5 V, V
SS
= AV
SS
= 0 V, Ta = –40 to 85°C, f(X
IN
) = 500 kHz to 8 MHz, in middle/high-speed mode unless otherwise noted)
10-bit A-D mode (when conversion mode selection bit (bit 0 of address 0014
16
) is “0”)
49
50
Symbol
Parameter
Limits
Typ.
Min.
Unit
Max.
10
±4
Test conditions
Resolution
Absolute accuracy
(excluding quantization error)
V
CC
= V
REF
= 3.0 to 5.5 V
Bits
LSB
35
150
tc(ADCLK)
(Note)
k
μ
A
μ
A
Conversion time
Ladder resistor
Reference power source input current
Analog port input current
t
CONV
R
LADDER
I
VREF
I
IA
12
50
100
200
5.0
V
REF
= 5 V
61
62
Note:
ADCLK is the control clock of the A-D converter. System clock
φ
is used.
Note:
ADCLK is the control clock of the A-D converter. System clock
φ
is used.
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