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參數(shù)資料
| 型號： | 7560 |
| 英文描述： | 7560 Group Datasheet Datasheet 1682K/JAN.14.03 |
| 中文描述： | 7560組數(shù)據(jù)表數(shù)據(jù)表1682K/JAN.14.03 |
| 文件頁數(shù)： | 51/90頁 |
| 文件大小： | 1682K |
| 代理商： | 7560 |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
50
Watchdog Timer
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software runaway).
The watchdog timer consists of an 8-bit watchdog timer L and a 6-
bit watchdog timer H. At reset or writing to the watchdog timer
control register (address 0037
16
), the watchdog timer is set to
“
3FFF
16
”
. When any data is not written to the watchdog timer con-
trol register (address 0037
16
) after reset, the watchdog timer is
stopped. The watchdog timer starts to count down from
“
3FFF
16
”
by writing to the watchdog timer control register and an internal re-
set occurs at an underflow. Accordingly, when using the watchdog
timer function, write the watchdog timer control register before an
underflow. The watchdog timer does not function when writing to
the watchdog timer control register has not been done after reset.
When not using the watchdog timer, do not write to it. When the
watchdog timer control register is read, the following values are
read:
G
value of high-order 6-bit counter
G
value of STP instruction disable bit
G
value of count source selection bit.
When the STP instruction disable bit is
“
0
”
, the STP instruction is
enabled. The STP instruction is disabled when this bit is set to
“
1
”
.
If the STP instruction which is disabled is executed, it is processed
as an undefined instruction, so that a reset occurs internally.
This bit can be set to
“
1
”
but cannot be set to
“
0
”
by program. This
bit is
“
0
”
after reset.
When the watchdog timer H count source selection bit is
“
0
”
, the
detection time is set to 8.19 s at f(X
CIN
) = 32 kHz and 32.768 ms
at f(X
IN
) = 8 MHz.
When the watchdog timer H count source selection bit is
“
0
”
, the
detection time is set to 32 ms at f(X
CIN
) = 32 kHz and 128
μ
s at
f(X
IN
) = 8 MHz. There is no difference in the detection time be-
tween the middle-speed mode and the high-speed mode.
Fig. 52 Block diagram of watchdog timer
Fig. 53 Structure of watchdog timer control register
Fig. 54 Timing of reset output
X
IN
Data bus
X
CIN
“
1
”
“
0
”
Internal
system clock
selection bit
(Note)
“
0
”
“
1
”
1/16
Watchdog timer H count
source selection bit
Reset circuit
Undefined instruction
Reset
“
3F
16
”
is set when
watchdog timer is
written to.
Internal reset
RESET
Reset release time wait
“
FF
16
”
is set when
watchdog timer is
written to.
STP instruction
STP instruction disable bit
Watchdog timer
H (6)
Watchdog timer
L (8)
Note: This is the bit 7 of CPU mode register and is used to switch the middle-/high-speed mode and low-speed mode.
b
7
b
0
W
(
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1
6
)
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T
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i
:
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d
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1
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:
:
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W
f
(
d
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)
t
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/
i
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d
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o
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r
r
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t
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)
t
u
/
s
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o
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o
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w
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i
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n
b
i
t
c
g
o
m
f
(
f
Watchdog timer H (for read-out of high-order 6 bit)
“
3FFF
16
”
is set to the watchdog timer by writing values to this address.
In
r
e
t
s
e
r
n
t
a
s
l
i
g
e
n
a
l
W
a
t
c
h
d
d
o
e
g
t
t
c
i
m
t
i
e
o
r
e
n
Approx. 1
ms
(f(X
IN
) = 8 MH
Z
)
f(
X
I
N
)
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