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參數(shù)資料
| 型號： | TUSB5052B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub |
| 中文描述： | USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器 |
| 文件頁數(shù)： | 70/84頁 |
| 文件大?。?/td> | 276K |
| 代理商： | TUSB5052B |
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9–2
9.1.3
IEPINT: Input Endpoint Interrupt Request Register
E7
E6
E5
E4
E3
E2
E1
E0
7
6
5
4
3
2
1
0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
BIT
NAME
RESET
FUNCTION
7–0
E[7:0]
0
These bits indicate which input endpoint interrupt is pending (IEP 7–0)
E[n] = 0
No interrupt pending (n = 7:0).
E[n] = 1
Indicates that the corresponding endpoint generated an interrupt. This is set by the hardware and is
cleared when the MCU writes to the VECINT register.
9.1.4
OEPINT: Output Endpoint Interrupt Request Register
E7
E6
E5
E4
E3
E2
E1
E0
7
6
5
4
3
2
1
0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
BIT
NAME
RESET
FUNCTION
7–0
E[7:0]
0
These bits indicate which input endpoint interrupt is pending (OEP 7–0).
E[n] = 0
No interrupt pending
E[n] = 1
Indicates that the corresponding endpoint generated an interrupt. This is set by the hardware and is
cleared when the MCU writes to the VECINT register.
9.1.5
VECINT: Vector Interrupt Register
This register contains a vector value, which identifies the internal interrupt source that trapped to location
0003H
.
Writing (any value) to this register removes the vector and updates the next vector value (if another interrupt is
pending). Note that the vector value is offset; therefore, its value is in increments of two (bit-0 is set to 0). When no
interrupt is pending, the vector is set to 00h (see Table 9–2). As shown, the interrupt vector is divided to two fields:
I[2:0] and G[3:0]. The I-field defines the interrupt source within a group (on a first-come-first-served basis). In the
G-field, which defines the group number, group G0 is the lowest, and G15 is the highest, priority.
G3
G2
G1
G0
I2
I1
I0
0
7
6
5
4
3
2
1
0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
BIT
NAME
RESET
FUNCTION
3–1
I[2:0]
0h
This field defines the interrupt source in a given group (see Table 9–2). Bit-0 = 0 always; therefore, vector values
are offset by two.
7–4
G[3:0]
0h
This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual interrupt vector.
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