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參數(shù)資料
| 型號： | TUSB5052B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub |
| 中文描述： | USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器 |
| 文件頁數(shù)： | 61/84頁 |
| 文件大?。?/td> | 276K |
| 代理商： | TUSB5052B |
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8–1
8 IEEE 1284 Parallel-Post
8.1
1284 Registers
Table 8-2 is a summary of the parallel-port modes of operations, and Figure 8–1 illustrates the data flow for output
and input transfers. A single PPDAT register is shared for output and input transfers; the RxF/TxE signal is used for
flow control. Table 8–1 summarizes the registers provided for configuration, status monitoring, and data I/O.
Table 8–3 summarizes the port signal definition.
Table 8–1. Parallel Port Registers
REGISTER NAME
ACCESS
MODE
FUNCTION
PPMCR
R/W
All
Mode control register
PPIMSK
R/W
All
Interrupt mask register
PPSTA
R/W
All
Status register
PPCTL
R/W
All
Control register
PPDAT
R/W
All
Data register
PPADR
R/W
2,3
EPP/ECP address register
Table 8–2. Parallel Port Mode Summary
MODE
DESCRIPTION
OUTPUTS
00
Centronics mode:
In this mode, the port direction is output only, and the DIR bit has no effect. The MCU writes data to
PPDAT and the control signals are generated by the MCU.
See Note 2
01
SPP mode (bidirectional auto Centronics ):
This is the bidirectional Centronics mode. In this mode, the port
direction can be changed by the DIR bit. The MCU or DMA writes data to PPDAT and the control signals are generated
automatically. This mode can support nibble operation.
See Note 2
10
ECP mode:
In the output direction (DIR = 0) data written to PPADR and to PPDAT are transmitted automatically using
the ECP protocol. In the input direction (DIR = 1), data bytes are transferred from the peripheral and placed in the
PPDAT register. CPU or DMA transfer is supported.
See Note 1
11
EPP mode:
In the output direction (DIR = 0) data written to PPADR and to PPDAT are transmitted automatically using
the EPP protocol. In the input direction (DIR = 1), data bytes are transferred from the peripheral and placed in the
PPDAT register. CPU or DMA transfer is supported.
1. 3-state CMOS output
±
14-mA drive/sink (control signals only)
2. Open-drain output –14-mA sink (control signals only)
See Note 1
NOTES:
PPDAT
PPDAT
TxE
RxF
DIR
PD (0–7)
Figure 8–1. P-Port Data I/O Flow
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