參數(shù)資料
型號： TUSB5052B
廠商： Texas Instruments, Inc.
英文描述： USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub
中文描述： USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器
文件頁數(shù)： 53/84頁
文件大?。?/td> 276K
代理商： TUSB5052B
7–5
7.1.6
MCR[2–1]: Modem-Control Register (2 Registers)
These registers provide control for modem interface I/O, and definition of the flow control mode.
LCD
LRI
RTS
RTR
SEN
LOOP
RCVE
URST
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIT
0
NAME
URST
RESET
0
FUNCTION
UART soft reset. This bit can be used by the MCU to reset the UART.
URST = 0
Normal operation. Writing a 0 by MCU has no effect.
URST = 1
When the MCU writes a 1 to this bit, a UART reset is generated (ORed with hard reset). When the
UART exits the reset state, URST is cleared. The MCU can monitor this bit to determine if the UART
completed the reset cycle.
1
RCVE
0
Receiver enable bit. This bit is valid only when 485E in FCRL is 1 (RS485 mode). When 485E = 0, this bit has no
effect on the receiver.
RCVE = 0
When 485E =1, the UART-receiver is disabled if RTS and DTR are active. (When data are
transmitted the UART-receiver is disabled.)
RCVE = 1
When 485 =1, the UART-receiver is enabled regardless of the RTS/DTR state (UART-receiver is on
all the time).
2
LOOP
0
This bit controls the normal/loop-back mode of operation (see Figure 7–1).
LOOP = 0
Normal operation
LOOP = 1
Enable loop-back mode of operation. In this mode the following occurs:
SOUT is set high.
SIN is disconnected.
The transmitter is looped back into the receiver.
The four modem-control inputs: CTS, DSR, DCD, and RI are disconnected.
DTR, RTS, LRI and LCD are internally connected to the four modem-control inputs, and read in the
MSR register as follows:
DTR is reflected in MSR[4] bit.
RTS is reflected in MSR[5] bit.
LRI is reflected in MSR[6] bit.
LCD is reflected in MSR[7] bit.
3
RSV
0
Reserved = 0
4
DTR
0
This bit controls the state of the DTR output pin (see Figure 7–1). This bit has no effect when auto-flow control is
used or when HDPX = 1 (in LCR register).
DTR = 0 Forces the DTR output pin to inactive (high)
DTR = 1 Forces the DTR output pin to active (low)
5
RTS
0
This bit controls the state of the RTS output pin (see Figure 7–1). This bit has no effect when auto-flow control is
used or when HDPX =1 (in LCR register).
RTS = 0 Forces the RTS output pin to inactive (high)
RTS = 1 Forces the RTS output pin to active (low)
6
LRI
0
This bit is used for loopback mode only. When in loopback mode, this bit is reflected in MSR[6]-bit (see Figure 7–1).
LRI = 0 Clears MSR[6] = 0
LRI = 1 Sets MSR[6] = 1
7
LCD
0
This bit is used for loopback mode only. When in loopback mode, this bit is reflected in MSR[7]-bit (see Figure 7–1).
LCD = 0 Clears MSR[7] = 0
LCD = 1 Sets MSR[7] = 1
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