參數(shù)資料
型號(hào)： TUSB5052B
廠商： Texas Instruments, Inc.
英文描述： USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub
中文描述： USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器
文件頁(yè)數(shù)： 55/84頁(yè)
文件大小： 276K
代理商： TUSB5052B
7–7
7.1.8
MSR[2–1]: Modem-Status Register (2 Registers)
These registers provide information about the current state of the control lines from the modem.
LCD
LRI
LDSR
LCTS
CD
TRI
DSR
CTS
7
6
5
4
3
2
1
0
R/O
R/O
R/O
R/O
R/C
R/C
R/C
R/C
BIT
NAME
CTS
RESET
FUNCTION
0
0
This bit indicates that CTS input has changed state. Cleared when the MCU reads the MSR register.
CTS = 0 Indicates no change in CTS input .
CTS = 1 Indicates that CTS input has changed state since the last time it was read. Clears when the MCU writes
a 1. Writing a 0 has no effect.
1
DSR
0
This bit indicates that DSR input has changed state. Cleared when the MCU reads the MSR register.
DSR = 0 Indicates no change in DSR input.
DSR = 1 Indicates that DSR input has changed state since the last time it was read. Clears when the MCU writes
a 1. Writing a 0 has no effect.
2
TRI
0
Trailing edge of the ring-indicator. This bit indicates that RI input has changed from low to high level. Cleared when
the MCU reads the MSR register.
RI = 0
Indicates that RI input is high.
RI = 1
Indicates that a transition from low to high level has occurred on RI * input. Clears when the MCU writes a
1. Writing a 0 has no effect.
3
CD
0
This bit indicates that CD input has changed state. Cleared when the MCU reads the MSR register.
DC = 0
Indicates no change in CD input.
DC = 1
Indicates that CD input has changed state since the last time it was read. Clears when thge MCU writes
a 1. Writing a 0 has no effect.
4
LCTS
0
During loopback, this bit reflects the status of MCR[1] (see Figure 7–1).
LCTS = 0 CTS input is high
LCTS = 1 CTS input is low
5
LDSR
0
During loopback, this bit reflects the status of MCR[0] (see
LDSR = 0 DSR input is high
LDSR = 1 DSR input is low
6
LRI
0
During loopback, this bit reflects the status of MCR[2] (see
LRI = 0
RI input is high
LRI = 1
RI input is low
7
LCD
0
During loopback, this bit reflects the status of MCR3] (see
LCD = 0
CD input is high
LCD = 1
CD input is low
7.1.9
DLL[2-1]: Divisor Register Low-Byte (2 Registers)
These registers contain the low-byte of the baud-rate divisor. The 1.8462-MHz clock is derived from the 48 MHz-clock
(dividing by 26). This clock is used for the baud-rate calculation (see Baud-Rate table)
D7
D6
D5
D4
D3
D2
D1
D0
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIT
NAME
RESET
FUNCTION
7
D[7:0]
08h
Low-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator.
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