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參數(shù)資料
| 型號(hào)： | TUSB5052B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub |
| 中文描述： | USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器 |
| 文件頁(yè)數(shù)： | 44/84頁(yè) |
| 文件大小： | 276K |
| 代理商： | TUSB5052B |
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6–4
6.1.3
DMACDR[4–3]: DMA Channel Definition Register (2 UART Receive Channels)
These registers are used to define the EDB number that the DMA uses for data transfer to the UARTS. In addition,
these registers define the data transfer direction and select X or Y as the transaction buffer.
EN
INE
CNT
XY
T/R
E2
R/W
E1
R/W
E0
R/W
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/O
BIT
NAME
RESET
FUNCTION
2–0
E[2:0]
0
End-point descriptor pointer. This field points to a set of EDB registers that is to be used for a given transfer.
3
T/R
0
This bit is always 1. This indicates that the DMA data transfer is from UART RDR register to SRAM. (The MCU can-
not change this bit.)
4
XY
0
XY Buffer select bit. Valid only when CNT = 0
XY = 0 Next buffer to transmit/receive is X
XY = 1 Next buffer to transmit/receive is Y
5
CNT
0
DMA Continuous transfer control bit. This bit defines the mode of the DMA transfer.
CNT = 0
Burst Mode:
DMA stops the transfer when the byte-count = 0 or when a receiver error occurs. At the end
of transfer, the high to low transition of EN interrupts the MCU (if enabled). In this mode, the XY bit is set
by the MCU to define the current buffer (X or Y).
CNT = 1
Continuous Mode:
In this mode, the DMA and UBM alternate between the X and Y buffers. The UBM
sets the XY bit and the DMA uses it for the transfer. The DMA alternates between the X/Y-buffers and
continues transmitting (from X/Y buffer) without MCU intervention. The DMA terminates, and interrupts
the MCU, under the following conditions:
1. Transaction time-out expired: DMA updates EDB and interrupts the MCU. UBM transfers the partial
packet to host.
2. UART receiver error condition: DMA updates EDB and does notinterrupt the MCU. UBM transfers the
partial packet to host.
6
INE
0
DMA Interrupt enable/disable bit. This bit is used to enable/disable the interrupt on transfer completion.
INE = 0
Interrupt is disabled. In addition, OVRUN and TXFT do not clear the EN-bit and the DMAC is not
disabled.
INE = 1
Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1 to 0 transition of the EN
bit. (When transfer is completed, EN = 0)
7
EN
0
DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When transfer completes, or when
terminated due to error, this bit is cleared. The 1 to 0 transition of this bit generates an interrupt (if interrupt is
enabled).
EN = 0
DMA is halted. The DMA is halted when transaction timeout occurs, or under a UART receiver-error
condition. When halted, the DMA updates the byte-count and sets NAK = 0 in IEDB. If the termination is
due to transaction time-out, the DMA generates an interrupt. However, if the termination is due to a UART
error condition, the DMA does not generate an interrupt. (The UART generates the interrupt.)
EN = 1
Setting this bit starts the DMA transfer.
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