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參數(shù)資料
| 型號： | TUSB5052B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub |
| 中文描述： | USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器 |
| 文件頁數(shù)： | 29/84頁 |
| 文件大?。?/td> | 276K |
| 代理商： | TUSB5052B |
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4–11
4.3.12 IEPSIZXY_n: Input Endpoint X/Y-Buffer Size (n = 1 to 7)
RSV
S6
R/W
S5
R/W
S4
R/W
S3
R/W
S2
R/W
S1
R/W
S0
R/W
7
6
5
4
3
2
1
0
R/O
BIT
NAME
RESET
FUNCTION
6–0
S[6:0]
x
X and Y-buffer size:
0000.0000b Count = 0
0000.0001b Count = 1 byte
:
:
0011.1111b Count = 63 bytes
0100.0000b Count = 64 bytes
Any value
≥
100.0001b may result in unpredictable results.
Reserved = 0
7
RSV
x
4.4
Endpoint-0 Descriptor Registers
Unlike registers EDB-1 to EDB-7, which are defined as memory entries in SRAM, endpoint-0 is described by a set
of 4 registers (two for output and two for input). The registers and their respective addresses, used for EDB-0
description, are defined in Table 4–6. EDB-0 has no Base-Address-Register since these addresses are hardwired
into FEF8 and FEF0. Note that the bit positions have been preserved to provide consistency with EDB-n
(n = 1 to 7).
Table 4–6. Input/Output EDB-0 Registers
ADDRESS
REGISTER NAME
DESCRITPION
BASE ADDRESS
FF83
FF82
OEPBCNT_0
OEPCNFG_0
Output endpoint_0: Byte count register
Output endpoint_0: Configuration register
FEF0
FF81
FF80
IEPBCNT_0
IEPCNFG_0
Input endpoint_0: Byte count register
Input endpoint_0: Configuration register
FEF8
4.4.1
IEPCNFG_0: Input Endpoint-0 Configuration Register
UBME
RSV
TOGLE
RSV
STALL
USBIE
RSV
RSV
7
6
5
4
3
2
1
0
R/W
R/O
R/O
R/O
R/W
R/W
R/O
R/O
BIT
NAME
RESET
FUNCTION
1–0
RSV
0
Reserved = 0
2
USBIE
0
USB interrupt enable on transaction completion. Set/cleared by the MCU.
USBIE = 0 No interrupt
USBIE = 1 Interrupt on transaction completion
3
STALL
0
USB stall condition indication. Set/cleared by the MCU
STALL = 0
STALL = 1
No stall
USB stall condition. If set by the MCU, a STALL handshake is initiated and the bit is cleared
automatically by the next setup transaction.
4
RSV
0
Reserved = 0
5
TOGLE
0
USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1
6
RSV
0
Reserved = 0
7
UBME
0
UBM enable/disable bit. Set/cleared by the MCU
UBME = 0 UBM cannot use this endpoint
UBME = 1 UBM can use this endpoint
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