參數(shù)資料
型號: TUSB5052B
廠商: Texas Instruments, Inc.
英文描述: USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub
中文描述: USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器
文件頁數(shù): 21/84頁
文件大?。?/td> 276K
代理商: TUSB5052B
4–3
Once the code is loaded, the MCU sets SDW = 1. This switches the memory map to normal-mode i.e. the 16K-RAM
is mapped to code space, and the MCU starts executing from location 0000h. Once the switch is done, the MCU sets
CONT = 1 (in the USBCTL register). This connectsthe device to the USB and results in normal USB device
enumeration.
4.1.3
GLOBCTL: Global Control Register
This register is used to control the MCU clock rate, power-down mode, and the CLKO frequency.
12/24
C1
C0
CLKOE
RSTP
RSV
RSV
RSV
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/O
R/O
R/O
BIT
2–0
3
NAME
RSV
RSTP
RESET
00b
1
FUNCTION
Reserved = 0
Reset-output polarity
RSTP = 0 RSTO output is active low
RSTP = 1 RSTO output is active high
0 = enable
1 = disable
Output clock frequency selection
00 = Output clock = 48 MHz
01 = Output clock = 24 MHz
10 = Output clock = 12 MHz
11 = Output clock = 6 MHz
4
CLKOE
0
6–5
C[1:0]
00b
7
12/24
0
This bit selects a 12 MHz or 24 MHz clock for the MCU
12/24=0 12 MHz
12/24=1 24 MHz
4.2
Buffers + I/O RAM Map
The address range from F800 to FFFF (2K bytes) is reserved for data buffers, setup packet, end-point descriptors
block (EDB) and all I/O. There are 128 location reserved for MMR (memory mapped registers). Table 4–2 represents
the XDATA space allocation and access restriction for the DMA, UBM and MCU.
Table 4–2. XDATA Space
DESCRIPTION
ADDRESS RANGE
UBM ACCESS
DMA ACCESS
MCU ACCESS
Internal MMRs
(memory mapped registers)
FFFF
FF80
No
(Only EDB-0)
No
(Only data register
and EDB-0)
Yes
EDB
FF7F
FF08
Only for
EDB update
Only for
EDB update
Yes
(end-point descriptors block)
FF07
FF00
Setup packet
Setu acket
Yes
No
Yes
FEFF
FEF8
Input end-point-0 buffer
In ut end oint 0 buffer
Yes
Yes
Yes
FEF7
FEF0
Output end-point-0 buffer
Out ut end oint 0 buffer
Yes
Yes
Yes
Data buffers
FEEF
F800
Yes
Yes
Yes
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