參數(shù)資料
型號(hào): TUSB5052B
廠商: Texas Instruments, Inc.
英文描述: USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub
中文描述: USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器
文件頁數(shù): 62/84頁
文件大?。?/td> 276K
代理商: TUSB5052B
8–2
Table 8–3. Parallel Port Signal Definition Summary
DRIVEN BY
SPP
EPP
ECP
I/O
PD[7:0]
PD[7:0]
PD[7:0]
TUSB5152
SLIN
ASTRB
SLIN
TUSB5152
STB
WRITE
HOSTCLK
TUSB5152
AFD
DSTRB
HOSTACK
TUSB5152
INIT
INIT
REVREQ
Peripheral
ACK
INTR
PERIPCLK
Peripheral
FALT
User Defined
PERIPREQ
Peripheral
SLCT
User Defined
User Defined
Peripheral
PER
User Defined
MPRIPREQ
Peripheral
BUSY
WAIT*
PERIPHACK
8.1.1
PPCNT: P-Port Counter Register
As a delay counter, this register records the time delay in 40 ns increments between assertion of the BUSY signal
and assertion of the STB signal. The same counter is also used for the STB pulse width.
D7
D6
D5
D4
D3
D2
D1
D0
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIT
NAME
RESET
FUNCTION
7–0
D[7:0]
12h
Delay and pulse counter for STB signal in 40ns increment.
8.1.2
PPMCR: P-Port Mode Control Register
This register is used to configure the port mode of operation. In addition, it provides bits that control the transfer
direction.
PEN
RSV
RSV
RSV
DIR
NBL
M1
M0
7
6
5
4
3
2
1
0
R/W
R/O
R/O
R/O
R/W
R/W
R/W
R/W
BIT
1–0
NAME
M[1:0]
RESET
00b
FUNCTION
Port mode definition. This field defines the P-port mode of operation (see Table 8–2 for more details).
00 =
Centronics mode. DIR bit has no effect. All control signals are generated by the MCU.
01 =
SPP mode: Bidirectional auto Centronics mode
10 =
EPP mode
11 =
ECP mode
2
NBL
0
Nibble mode control bit. This bit is valid only in SPP mode.
NBL = 0 SPP is in byte mode.
NBL = 1 SPP is in nibble mode.
3
DIR
0
Transfer direction bit. Valid for modes 1 to 3.
DIR = 0
The PPDAT drives PD[7:0] data bus (transmitter).
DIR = 1
PD[7:0] data bus is input to PPDAT register (receiver).
6–4
RSV
0
Reserved = 0
7
PEN
0
PP enable bit. This bit is used by the MCU to enable/disable the P-port data transfer in all modes.
PEN = 0 The PP is disabled. Data transfer (via DMA or MCU) cannot take place. To terminate PP transfers, the
MCU must clear this bit.
PEN = 1 The PP is enabled and data transfer (via DMA or MCU) can take place.
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