參數(shù)資料
型號： TUSB5052B
廠商： Texas Instruments, Inc.
英文描述： USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub
中文描述： USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器
文件頁數(shù)： 51/84頁
文件大小： 276K
代理商： TUSB5052B
7–3
7.1.4
FCRL[2–1]: UART Flow Control Register (2 Registers)
These registers provide the flow-control modes of operation (see Table 7–3).
485E
DTR
RTS
RXOF
DSR
CTS
TXOA
TXOF
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIT
0
NAME
TXOF
RESET
0
FUNCTION
This bit controls the transmitter Xon/Xoff flow control.
TXOF = 0
Disable transmitter Xon/Xoff flow control
TXOF = 1
Enable transmitter Xon/Xoff flow control
1
TXOA
0
This bit controls the transmitter Xon-on-any/Xoff flow control.
TXOA = 0
Disable the transmitter Xon-on-any/Xoff flow control
TXOA = 1
Enable the transmitter Xon-on-any/Xoff flow control
2
CTS
0
Transmitter CTS flow-control enable bit.
CTS = 0
Disables transmitter CTS flow control.
CTS = 1
CTS flow control is enabled, i.e., when CTS input pin is high, transmission is halted; when CTS pin is
low, transmission resumes.
3
DSR
0
Transmitter DSR flow control enable bit.
DSR = 0
Disables transmitter DSR flow control.
DSR = 1
DSR flow control is enabled, i.e., when DSR input pin is high, transmission is halted; when DSR pin is
low, transmission resumes.
4
RXOF
0
This bit controls the receiver Xon/Xoff flow control.
RXOF = 0
Receiver does not attempt to match Xon/Xoff characters.
RXOF = 1
Receiver searches for Xon/Xoff characters.
5
RTS
0
Receiver RTS flow control enable bit
RTS = 0
Disables receiver RTS flow control.
RTS = 1
Receiver RTS flow control is enabled. RTS output pin goes high when the receiver FIFO HALT
trigger level is reached; it goes low, when the receiver FIFO RESTORE receiving trigger level is
reached.
6
DTR
0
Receiver DTR flow control enable bit
DTR = 0
Disables receiver DTR flow control.
DTR = 1
Receiver DTR flow control is enabled. DTR output pin goes high when the receiver FIFO HALT
trigger level is reached; it goes low, when the receiver FIFO RESTORE receiving trigger level is
reached.
7
485E
0
RS485 enable bit. This bit is used to configure the UARTs to control external RS485 transceivers. When configured
in half-duplex mode, RTS and DTR are used to enable the RS485 driver and receiver (see Figure12–2).
485E = 0
UART is in normal operation mode (full duplex).
485E = 1
The UART is in RS485 mode. In this mode RTS and DTR are active with opposite polarity (when
RTS = 0, DTR = 1 ). When the DMA is ready to transmit, it asserts RTS = 0 (and DTR = 1) 2-bit-time
before transmission starts. When DMA terminates the transmission, it de-asserts RTS = 1 (and
DTR = 0) as soon as possible after transmission stops. When 485E is set to 1, the DTR and RTS bits
in the MCR register have no effect.
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