參數(shù)資料
型號(hào)： TUSB5052B
廠商： Texas Instruments, Inc.
英文描述： USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub
中文描述： USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器
文件頁(yè)數(shù)： 43/84頁(yè)
文件大?。?/td> 276K
代理商： TUSB5052B
6–3
6.1.2
DMACSR[2–1]: DMA Control and Status Register (2 UART Transmit Channels)
This register is used to define the transaction-timeout value. In addition, it contains a completion code that reports
any errors or a time-out condition.
TEN
C4
C3
C2
C1
C0
TXFT
PPKT
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/C
R/C
BIT
0
NAME
PPKT
RESET
0
FUNCTION
Partial packet condition bit. This bit is set by the DMA and cleared by the MCU (see Table 6–2).
PPKT = 0
No partial-packet condition
PPKT = 1
Partial-packet condition detected. When IEN =0, this bit does not clear the EN bit in DMACDR;
therefore, the DMAC stays enabled, ready for the next transaction. Clears when MCU writes a 1.
Writing a 0 has no effect.
1
TXFT
0
Transfer time-out condition (see Table 6–2)
TXFT = 0
DMA stopped transfer without time-out
TXFT = 1
DMA stopped due to transaction timeout. When IEN = 0, this bit does not clear the EN bit in
DMACDR; therefore, the DMAC stays enabled, ready for the next transaction. DMA clears when the
MCU writes a 1. Writing a 0 has no effect.
6-2
C[4:0]
0
This field is used to define the transaction time-out value in 1ms increments. This value is loaded to a down counter
every time a byte transfer occurs. The down counter is decremented every SOF pulse (1ms). If the counter
decrements to zero it sets TXFT = 1 (in DMACSR register) and halts the DMA transfer. The counter starts counting
only when TEN = 1 and EN = 1 (in DMACDR
)
and the first byte has been transmitted See Figure 6–1).
00000 = 0 ms time-out
:
:
11111 = 31ms time-out
7
TEN
0
Transaction time-out counter enable/disable bit
TEN = 0 Counter is disabled (does nottime out).
TEN = 1 Counter is enabled.
Table 6–2. DMA OUT-Termination Condition
OUT-TERMINATION
TXFT
PPKT
COMMENTS
UART partial-packet
0
1
This condition occurs when host sends a partial packet.
UART time-out
1
0
This condition occurs when X & Y output-buffers are full and the UART transmitter cannot trans-
mit (due to flow-control restriction) or if host has no data to transmit.
Counter
C (0–4)
TXFT
Load
SOF
TEN
EN
Figure 6–1. Transaction Time-Out Diagram
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