參數(shù)資料
型號(hào)： TUSB5052B
廠商： Texas Instruments, Inc.
英文描述： USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub
中文描述： USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器
文件頁(yè)數(shù)： 54/84頁(yè)
文件大小： 276K
代理商： TUSB5052B
7–6
7.1.7
LSR[2–1]: Line-Status Register (2 Registers)
These registers provide the status of the data transfer. DMA transfer is halted when any of OVR, PTE, FRE, BRK
or EXIT is 1.
RSV
RSV
TxE
RxF
BRK
FRE
PTE
OVR
7
6
5
4
3
2
1
0
R/O
R/O
R/O
R/O
R/C
R/C
R/C
R/C
BIT
NAME
RESET
FUNCTION
0
OVR
0
This bit indicates the overrun condition of the receiver. If set, it halts the DMA transfer and generates a status
interrupt (if enabled).
OVR = 0 No overrun error
OVR = 1 Overrun error has occurred. Clears when the MCU writes a 1. Writing a 0 has no effect.
1
PTE
0
This bit indicates the parity condition of the received byte. If set, it halts the DMA transfer and generates a status
interrupt (if enabled).
PTE = 0 No parity error in data received
PTE = 1 Parity error in data received. Clears when the MCU writes a 1. Writing a 0 has no effect.
2
FRE
0
This bit indicates the framing condition of the received byte. If set, it halts the DMA transfer and generates a status
interrupt (if enabled).
FRE = 0 No framing error in data received
FRE = 1 Framing error in data received. Clears when MCU writes a 1. Writing a 0 has no effect.
3
BRK
0
This bit indicates the break condition of the received byte. If set, it halts the DMA transfer and generates a status
interrupt (if enabled).
BRK = 0 No break condition
BRK = 1 A break condition in data received was detected. Clears when the MCU writes a 1. Writing a 0 has no
effect.
4
RxF
0
This bit indicates the condition of the receiver data register. Typically, the MCU does not monitor this bit since data
transfer is done by the DMA controller.
RxF = 0
No data in the RDR
RxF = 1
RDR contains data. Generates Rx interrupt (if enabled).
5
TxE
1
This bit indicates the condition of the transmitter data register. Typically, the MCU does not monitor this bit since
data transfer is done by the DMA controller.
TxE = 0
TDR is notempty
TxE = 1
TDR is empty. Generates Tx interrupt (if enabled).
6, 7
RSV
0
Reserved =0
CTS
DSR
RI
DCD
(4) LCTS
(5) LDSR
(6) LRI
(7) LCD
(4) DTR
(5) RTS
(6) LRI
(7) LCD
(2) LOOP
DTR
RTS
MSR
MCR
Figure 7–1. MSR and MCR Registers in Loopback Mode
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