參數資料
型號: TUSB5052B
廠商: Texas Instruments, Inc.
英文描述: USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub
中文描述: USB轉2 -串行接口1 -可配置可選并行控制器集線器
文件頁數: 24/84頁
文件大?。?/td> 276K
代理商: TUSB5052B
4–6
Table 4–4. EDB Memory Locations
ADDRESS
REGISTER
DESCRIPTION
FF78
IEPCNF_7
Input Endpoint_7: Configuration
FF70
IEPCNF_6
Input Endpoint_6: Configuration
FF68
IEPCNF_5
Input Endpoint_5: Configuration
FF60
IEPCNF_4
Input Endpoint_4: Configuration
FF58
IEPCNF_3
Input Endpoint_3: Configuration
FF50
IEPCNF_2
Input Endpoint_2: Configuration
FF48
IEPCNF_1
Input Endpoint_1: Configuration
FF47
FF40
RESERVED
FF38
OEPCNF_7
Output Endpoint_7: Configuration
FF30
OEPCNF_6
Output Endpoint_6: Configuration
FF28
OEPCNF_5
Output Endpoint_5: Configuration
FF20
OEPCNF_4
Output Endpoint_4: Configuration
FF18
OEPCNF_3
Output Endpoint_3: Configuration
FF10
OEPCNF_2
Output Endpoint_2: Configuration
FF08
OEPCNF_1
Output Endpoint_1: Configuration
FF07
FF00
(8-bytes)
Setup packet block
FEFF
FEF8
(8-bytes)
Input Endpoint-0 buffer
FEF7
FEF0
(8-bytes)
Output End-point-0 buffer
FEEF
F800
TOPBUFF
Top of buffer space
Buffer space
STABUFF
Start of buffer space
4.3
Endpoint Descriptor Block (EDB-1 to EDB-7)
Data transfers between the USB, the MCU and external devices are defined by an endpoint descriptor block (EDB).
Eight input- and eight output-EDBs are provided. With the exception of EDB-0 (I/O Endpoint-0), all EDBs are located
in SRAM as per Table 4–4. Each EDB contains information describing the X and Y buffers. In addition, each EDB
provides general status information.
Table 4–5 illustrates the EDB entries for EDB-1 to EDB-7. EDB-0 registers will be described separately.
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