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參數(shù)資料
| 型號(hào)： | TUSB5052B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | USB to 2-Serial + 1-Parallel Controller With Configurable Optional Hub |
| 中文描述： | USB轉(zhuǎn)2 -串行接口1 -可配置可選并行控制器集線器 |
| 文件頁數(shù)： | 69/84頁 |
| 文件大?。?/td> | 276K |
| 代理商： | TUSB5052B |
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9–1
9 Interrupts
9.1
8052 Interrupt and Status Registers
All 8052-standard, 5-interrupt sources are preserved. SIE is the standard interrupt-enable register that controls the
five interrupt sources. All the additional interrupt sources are ORed together to generate EX0. The XINTO signal is
provided to interrupt an external MCU (see interrupt connection diagram).
Table 9–1. 8052 Interrupt Location Map
INTERRUPT
SOURCE
DESCRIPTION
START
ADDRESS
COMMENTS
ES
UART interrupt
0023H
ET1
Timer-1 interrupt
001BH
EX1
External interrupt-1
0013H
ET0
Timer-0 interrupt
000BH
EX0
External interrupt-0
0003H
Used for all internal peripherals
Reset
0000H
9.1.1
8052 Standard Interrupt Enable Register
EA
RSV
RSV
ES
ET1
EX1
ET0
EX0
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIT
NAME
RESET
FUNCTION
0
EX0
0
Enable or disable external interrupt-0
EX0 = 0
External interrupt-0 is disabled.
EX0 = 1
External interrupt-0 is enabled.
1
ET0
0
Enable or disable timer-0 interrupt
ET0 = 0
Timer-0 interrupt is disabled.
ET0 = 1
Timer-0 interrupt is enabled.
2
EX1
0
Enable or disable external interrupt-1
EX1 = 0
External interrupt-1 is disabled.
EX1 = 1
External interrupt-1 is enabled.
3
ET1
0
Enable or disable timer-1 interrupt
ET1 = 0
Timer-1 interrupt is disabled.
ET1 = 1
Timer-1 interrupt is enabled.
4
ES
0
Enable or disable serial port interrupts
ES = 0
Serial-port interrupt is disabled.
ES = 1
Serial-port interrupt is enabled.
5, 6
RSV
0
Reserved
7
EA
0
Enable or disable all interrupts (global disable)
EA = 0
Disable all interrupts.
EA = 1
Each interrupt source is individually controlled.
9.1.2
Additional Interrupt Sources
All non-standard 8052 interrupts (DMA, I
2
C, etc.) are ORed to generate an internal INT0. Note: the externalINT0 is
notused. Furthermore, the INT0 must be programmed as an active, low-level interrupt (not edge-triggered). A vector
interrupt register is provided to identify all interrupt sources (see vector-interrupt register definition). Up to 64 interrupt
vectors are provided. It is the responsibility of the MCU to read the vector and dispatch to the proper interrupt routine.
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