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參數(shù)資料
| 型號： | TMX320DM6446ZWT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media System on-Chip |
| 中文描述： | 數(shù)字媒體系統(tǒng)芯片 |
| 文件頁數(shù)： | 86/214頁 |
| 文件大?。?/td> | 1699K |
| 代理商： | TMX320DM6446ZWT |
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www.ti.com
P
5.2
Recommended Clock and Control Signal Transition Behavior
5.3
Power Supplies
5.3.1
Power-Supply Sequencing
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
5.1.1.2
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do
not
include delays by board routings. As a
good board design practice, such delays must
always
be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the
Using IBIS Models for Timing
Analysis
application report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
All clocks and control signals should transition between V
IH
and V
IL
(or between V
IL
and V
IH
) in a
monotonic manner.
For more information regarding TI's power management products and suggested devices to power TI
DSPs, visit
www.ti.com/dsppower
.
Note:
This power sequencing information is preliminary and subject to change.
Currently, DM6446 devices do not require specific power sequencing between the core supply and the I/O
supply. However, systems should be designed to ensure that neither supply is powered up for extended
periods of time(>1 second) if the other supply is below the proper operating voltage.
5.3.1.1
Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the DM6446 device, the PC board should include separate power planes for core,
I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
5.3.1.2
Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to DM6446. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for
the core supplies and 30 for the I/O supplies. These caps need to be close to the DM6446 power pins, no
more than 1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better
because of their lower parasitic inductance. Proper capacitance values are also important. Small bypass
caps (near 560 pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can
be obtained in a small package) should be next closest. TI recommends no less than 8 small and
8 medium caps per supply be placed immediately next to the BGA vias, using the "interior" BGA space
and at least the corners of the "exterior".
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 100
μ
F) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of
any component, verification of capacitor availability over the product’s production lifetime should be
considered.
Peripheral and Electrical Specifications
86
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