參數(shù)資料
型號(hào)： TMX320DM6446ZWT
廠商： Texas Instruments, Inc.
英文描述： Digital Media System on-Chip
中文描述： 數(shù)字媒體系統(tǒng)芯片
文件頁(yè)數(shù)： 32/214頁(yè)
文件大?。?/td> 1699K
代理商： TMX320DM6446ZWT
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www.ti.com
P
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
Table 2-13. EMIFA Terminal Functions (continued)
SIGNAL
NAME
IPD/
IPU
(2)
TYPE
(1)
DESCRIPTION
NO.
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF. For
NAND/SmartMedia/xD or EMIFA, it is write enable output EM_WE.
For NAND/SmartMedia/xD, it is write enable output (WE).
For CF, it is write strobe output (IOWR).
For ATA, it is write strobe output DIOW.
This pin is multiplexed between EMIFA and ATA/CF. For EMIFA, this is the Bank
Address 0 output (EM_BA[0]). When connected to an 8-bit asynchronous memory,
this pin is the lowest order bit of the byte address. When connected to a 16-bit
asynchronous memory, this pin has the same function as EMIF address pin 22
(EM_A[22]).
For ATA/CF, it is Device address bit 0 output DA0.
This pin is multiplexed between EMIFA, ATA/CF, and GPIO. For EMIFA, this is
the Bank Address 1 output EM_BA[1]. When connected to a 16 bit asynchronous
memory this pin is the lowest order bit of the 16-bit word address. When
connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the address.
For ATA/CF, it is Device address bit 1 output DA1.
In GPIO mode, it is GPIO52.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is
address bit 21 output EM_A[21].
For GPIO, it is GPIO10.
For VLYNQ, it is bit 0 of the transmit bus VLYNQ_TXD0.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is
address bit 20 output EM_A[20].
For GPIO, it is GPIO11.
For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is
address bit 19 output EM_A[19].
For GPIO, it is GPIO12.
For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is
address bit 18 output EM_A[18].
For GPIO, it is GPIO13.
For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is
address bit 17 output EM_A[17].
For GPIO, it is GPIO14.
For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is
address bit 16 output EM_A[16].
For GPIO, it is GPIO15.
For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is
address bit 15 output EM_A[15].
For GPIO, it is GPIO16.
For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is
address bit 14 output EM_A[14].
For GPIO, it is GPIO17.
For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3.
This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 13
output EM_A[13].
For GPIO, it is GPIO18.
This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 12
output EM_A[12].
For GPIO, it is GPIO19.
This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 11
output EM_A[11].
For GPIO, it is GPIO20.
This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 10
output EM_A[10].
For GPIO, it is GPIO21.
EM_WE
(WE)
(IOWR)/
DIOW
G2
I/O/Z
IPD
EM_BA[0]/
DA0
J3
I/O/Z
IPD
EM_BA[1]/
DA1/
GPIO52
H2
I/O/Z
IPD
EM_A[21]/
GPIO10/
VLYNQ_TXD0
T3
I/O/Z
IPD
EM_A[20]/
GPIO11/
VLYNQ_RXD0
R3
I/O/Z
IPD
EM_A[19]/
GPIO12/
VLYNQ_TXD1
R4
I/O/Z
IPD
EM_A[18]/
GPIO13/
VLYNQ_RXD1
P5
I/O/Z
IPD
EM_A[17]/
GPIO14/
VLYNQ_TXD2
R2
I/O/Z
IPD
EM_A[16]/
GPIO15/
VLYNQ_RXD2
R5
I/O/Z
IPD
EM_A[15]/
GPIO16/
VLYNQ_TXD3
P3
I/O/Z
IPD
EM_A[14]/
GPIO17/
VLYNQ_RXD3
P4
I/O/Z
IPD
EM_A[13]/
GPIO18
N4
I/O/Z
IPD
EM_A[12]/
GPIO19
R1
I/O/Z
IPD
EM_A[11]/
GPIO20
P2
I/O/Z
IPD
EM_A[10]/
GPIO21
P1
I/O/Z
IPD
32
Device Overview
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