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| 型號(hào)： | TMX320DM6446ZWT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media System on-Chip |
| 中文描述： | 數(shù)字媒體系統(tǒng)芯片 |
| 文件頁(yè)數(shù)： | 3/214頁(yè) |
| 文件大小： | 1699K |
| 代理商： | TMX320DM6446ZWT |
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TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
TMS320C6000 DSP platform. It is based on an enhanced version of the second-generation
high-performance,
advanced
very-long-instruction-word
Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a
code-compatible member of the C6000 DSP platform. The TMS320C64x+ DSP is an enhancement of
the C64x+ DSP with added functionality and an expanded instruction set.
(VLIW)
architecture
developed
by
Texas
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and
C64x+ CPU, respectively.
With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the
C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The
eight functional units include instructions to accelerate the performance in video and imaging applications.
The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million
MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details
on the C64x+ DSP, see the
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide
(literature number SPRU732).
The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level
cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the
Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)
consists of an 512K-bit memory space that is shared between program and data space. L2 memory can
be configured as mapped memory, cache, or combinations of the two.
The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a
Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio
serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers;
1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable
interrupt/event generation modes, multiplexed with other peripherals;
handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory
interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a
higher speed synchronous memory interface for DDR2.
3
UARTs
with
hardware
The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging
peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing
Back-End (VPBE) output with imaging co-processor (VICP) used for display.
The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine
(Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The
CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices
(CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS
sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules
provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image
data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is
between 64 and 1024.
The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a
Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate
OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window
allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz,
providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC
also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of
8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.
Digital Media System-on-Chip (DMSoC)
3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320DM6467TZUT1 | 制造商:Texas Instruments 功能描述: |
| TMX320DM6467ZUT | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Dig Media System-on- Chip RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMX320DM647ZUT720 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Digital Media Processor |
| TMX320DM647ZUT900 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Digital Media Processor |
| TMX320DM648ACUT7 | 制造商:Texas Instruments 功能描述:- Trays |
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