![](http://datasheet.mmic.net.cn/370000/TMX320DM6446ZWT_datasheet_16742798/TMX320DM6446ZWT_45.png)
www.ti.com
P
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
Table 2-24. VPBE Terminal Functions (continued)
SIGNAL
IPD/
IPU
(2)
TYPE
(1)
DESCRIPTION
NAME
NO.
BTSEL1
0
0
1
1
This pin is multiplexed between EMIFA and the VPBE. At reset, the input
state is sampled to set the EMIFA data bus width (EM_WIDTH). For an
8-bit wide EMIFA data bus, EM_WIDTH = 0 [default]. For a 16-bit wide
EMIFA data bus, EM_WIDTH = 1.
After reset, it is video encoder output COUT2 or RGB666/888 Blue output
data bit 5 B5.
This pin is multiplexed between DSP boot and the VPBE. At reset, the
input state is sampled to set the DSP boot source DSP_BT. The DSP is
booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when
DSP_BT=1.
After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit
6 output B6.
BTSEL0
0
1
0
1
ARM Boot Mode
ARM ROM Boot (NAND) [default]
ARM EMIFA Boot (NOR)
Reserved
ARM ROM Boot (UART)
COUT1/
B4/
BTSEL1
B16
I/O/Z
IPD
COUT2/
B5/
EM_WIDTH
A17
I/O/Z
IPD
COUT3/
B6/
DSP_BT
B17
I/O/Z
IPD
COUT4/
B7
COUT5/
G2
COUT6/
G3
COUT7/
G4
YOUT0/
G5/
AEAW0
YOUT1/
G6/
AEAW1
YOUT2/
G7/
AEAW2
YOUT3/
R3/
AEAW3
YOUT4/
R4/
AEAW4
YOUT5/
R5
YOUT6/
R6
YOUT7/
R7
A18
I/O/Z
IPD
Video encoder output COUT4 or RGB666/888 Blue data bit 7 output B7.
B18
I/O/Z
IPD
Video encoder output COUT5 or RGB666/888 Green data bit 2 output G2.
B19
I/O/Z
IPD
Video encoder output COUT6 or RGB666/888 Green data bit 3 output G3.
C16
I/O/Z
IPD
Video encoder output COUT7 or RGB666/888 Green data bit 4 output G4.
D15
I/O/Z
IPD
D16
I/O/Z
IPD
These pins are multiplexed between EMIFA and the VPBE. At reset, the
input states of AEAW[4:0] are sampled to set the EMIFA address bus
width. See the Peripheral Selection at Device Reset section for details.
After reset, these are video encoder outputs YOUT[0:4] or RGB666/888
Red and Green data bit outputs G5, G6, G7, R3, and R4.
D17
I/O/Z
IPD
D18
I/O/Z
IPD
E15
I/O/Z
IPD
E16
I/O/Z
IPD
Video encoder output YOUT5 or RGB666/888 Red data bit 5 output R5.
E17
I/O/Z
IPD
Video encoder output YOUT6 or RGB666/888 Red data bit 6 output R6.
E18
I/O/Z
IPD
Video encoder output YOUT7 or RGB666/888 Red data bit 7 output R7.
This pin is multiplexed between GPIO and the VPBE. In GPIO mode, it is
GPIO pin GPIO0.
In VPBE mode, it is the LCD output enable LCD_OE.
This pin is multiplexed between GPIO and the VPBE. In GPIO mode, it is
GPIO pin GPIO2.
In VPBE mode, it is RGB888 Green data bit 0 output G0.
This pin is multiplexed between GPIO, and the VPBE. In GPIO mode, it is
GPIO pin GPIO3.
In VPBE mode, it is RGB888 Blue data bit 0 output B0.
or LCD interlaced output LCD_FIELD.
GPIO0/
LCD_OE
C13
I/O/Z
IPD
GPIO2/
G0
D13
I/O/Z
IPD
GPIO3/
B0/
LCD_FIELD
C14
I/O/Z
IPD
Device Overview
45