參數(shù)資料
型號(hào): TMX320DM6446ZWT
廠(chǎng)商: Texas Instruments, Inc.
英文描述: Digital Media System on-Chip
中文描述: 數(shù)字媒體系統(tǒng)芯片
文件頁(yè)數(shù): 209/214頁(yè)
文件大小: 1699K
代理商: TMX320DM6446ZWT
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5.24
IEEE 1149.1 JTAG
5.24.1
JTAG ID Register Description
5.24.2
JTAG Peripheral Register Description(s)
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
The JTAG
(1)
interface is used for BSDL testing and emulation of the DM6446 device.
The DM6446 device requires that both TRST and RESET be asserted upon power up to be properly
initialized. While RESET initializes the device, TRST initializes the device's emulation logic. Both resets
are required for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and
must
be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
For maximum reliability, DM6446 includes an internal pulldown (IPD) on the TRST pin to ensure that
TRST will always be asserted upon power up and the device's internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to intialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations. Following the release of
RESET, the low-to-high transition of TRST must be "seen" to latch the state of EMU1 and EMU0. The
EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed
information, see the terminal functions section of this data sheet.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
(1)
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
DM6446 device, the JTAG ID register resides at address location 0x01C4 0028. The register hex value for
DM6446 is: 0x0B70 002F. For the actual register bit names and their associated bit field descriptions, see
Figure 5-71
and
Table 5-103
.
31-28
27-12
11-1
0
VARIANT (4-Bit)
PART NUMBER (16-Bit)
MANUFACTURER (11-Bit)
LSB
R-0000
R-1011 0111 0000 0000
R-0000 0010 111
R-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 5-71. JTAG ID Register Description - DM6446 Register Value - 0xXB70 001F
Table 5-103. JTAG ID Register Selection Bit Descriptions
BIT
31:28
27:12
11-1
0
NAME
VARIANT
PART NUMBER
MANUFACTURER
LSB
DESCRIPTION
Variant (4-Bit) value. DM6446 value: 0000.
Part Number (16-Bit) value. DM6446 value: 1011 0111 0000 0000.
Manufacturer (11-Bit) value. DM6446 value: 0000 0010 111.
LSB. This bit is read as a "1" for DM6446.
Peripheral and Electrical Specifications
209
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