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P
5.4
Reset
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
Table 5-5. Characteristics of the Power-Down Modes
POWER-
DOWN
MODE
Standby
TRIGGER/ENTRY
WAKE-UP METHOD
EFFECT ON CHIP'S OPERATION
PSC, System Module, PLLC1/2,
DDR2 Memory Controller, ARM
Wait For Interrupt instruction
Interrupts
This mode consumes the lowest power,
with the minimum set of modules kept
alive that are required to wake up the
chip to a higher power mode. DSP and
coprocessor subsystems are not
powered. The rest of the chip is
powered and clocks are suspended,
except for GPIO (interrupts), UARTs,
I2C (in slave mode), and Ethernet MAC.
PLLs are operating in bypass mode.
27-MHz clock is the only clock available
to the system. DDR2 clock is suspended
and DDR2 is put into self-refresh mode.
This mode is for ARM to sustain some
basic control functions. DSP and
coprocessor subsystems are not
powered. The rest of the chip is
powered, but most clocks are
suspended, except for ARM, GPIO,
UARTs, SPI, I2C, PWMs, and Timers.
PLLs are operating in bypass mode.
27-MHz clock is the only clock available
to the system. ARM runs at 13.5 MHz,
and handles all peripherals by direct
access. DDR2 clock is suspended and
DDR2 is put into self-refresh mode.
ARM will not have access to DDR2 and
its caches are either frozen or
inaccessible.
This mode is for Digital Still Camera
(DSC) preview. DSP and coprocessor
subsystems are not powered. The rest
of the chip is powered, and the PLLs are
operating to support the activities
needed for preview processing and data
flow. ARM and DDR2 EMIF operate at
nominal frequencies.
The entire chip is powered. All modules
operate at nominal clock frequency.
Unused peripherals have their clocks
suspended. Active peripherals have
their clocks suspended when unneeded.
Low Power
PSC, System Module, PLLC1/2,
DDR2 Memory Controller
Interrupts
Preview
PSC, System Module, PLLC1/2
Interrupts
Active
PSC, System Module, PLLC1/2
N/A
5.3.1.6
DM6446 Power-Down Mode with an Emulator
TBD
DM6446 supports various types of resets. Power-on-reset (POR), warm reset, max reset, system reset,
C64x+ local reset, and module reset are summarized in
Table 5-6
.
Table 5-6. DM6446 Resets
Type
Power-on-reset (POR)
Initiator
RESET pin active low while TRST is low.
Description
Global chip reset (Cold reset). Activates the POR signal
on chip, which is used to reset test and emulation logic.
Resets everything except for test and emulation logic.
ARM emulator stays alive during warm reset, but the
C64x+ emulator does not.
Same as Warm reset, except for initiators.
Warm reset
RESET pin active low while TRST is high.
Maximum reset
Emulator, WD Timer
Peripheral and Electrical Specifications
95