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P
1.2
Description
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
External Memory Interfaces (EMIFs)
–
32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
–
Asynchronous16-Bit Wide EMIF (EMIFA)
With 128M-Byte Address Reach
Flash Memory Interfaces
NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
Flash Card Interfaces
–
Multimedia Card (MMC)/Secure Digital (SD)
–
CompactFlash Controller With True IDE
Mode
–
SmartMedia
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
One 64-Bit Watch Dog Timer
Three UARTs (One with RTS and CTS Flow
Control)
One Serial Port Interface (SPI) With Two
Chip-Selects
Master/Slave Inter-Integrated Circuit (I
2
C
Bus)
Audio Serial Port (ASP)
–
I2S
–
AC97 Audio Codec Interface
–
Standard Voice Codec Interface (AIC12)
10/100 Mb/s Ethernet MAC (EMAC)
–
IEEE 802.3 Compliant
–
Media Independent Interface (MII)
VLYNQ Interface (FPGA Interface)
USB Port With Integrated 2.0 PHY
–
USB 2.0 High-/Full-Speed (480-Mbps) Client
–
USB 2.0 High-/Full-/Low-Speed Host
(Mini-Host, Supporting One External
Device)
Three Pulse Width Modulator (PWM) Outputs
On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash or UART
ATA/ATAPI I/F (ATA/ATAPI-5 Specification)
Individual Power-Saving Modes for ARM/DSP
Flexible PLL Clock Generators
IEEE-1149.1 (JTAG) Boundary-
Scan-Compatible
Up to 71 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
361-Pin Pb-Free BGA Package
(ZWT Suffix), 0.8-mm Ball Pitch
0.09-μm/6-Level Cu Metal Process (CMOS)
3.3-V and 1.8-V I/O, 1.2-V Internal
Applications:
–
Digital Media
–
Networked Media Encode/Decode
–
Video Imaging
The TMS320DM6446 (also referenced as DM6446) leverages TI’s Davinci technology to meet the
networked media encode and decode application processing needs of next-generation embedded devices.
The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, high processing performance, and long battery life through the
maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set
Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an
ARM926EJ-S MPU core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core incorporates:
A coprocessor 15 (CP15) and protection module
Data and program Memory Management Units (MMUs) with table look-aside buffers.
Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual
index virtual tag (VIVT).
The
TMS320C64x+
DSPs
are
the
highest-performance
fixed-point
DSP
generation
in
the
2
Digital Media System-on-Chip (DMSoC)