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P
2.3.11
Power and Sleep Controller (PSC)
2.3.12
ARM Interrupt Controller (AINTC)
2.3.13
System Module
2.3.14
Power Management
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
The ARM Subsystem includes the Power and Sleep Controller (PSC). Through register settings
accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating
and power domain shut-off. Brief details on the PSC are given in the Power Supply section. For more
detailed information and complete register descriptions for the PSC, see the Documentation Support
section of this document for the ARM Subsystem Guide.
The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ
(interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this
document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see the
Documentation Support section of this document for the ARM Subsystem Guide.
The ARM Subsystem includes the System module. The System module consists of a set of registers for
configuring and controlling a variety of system functions. For details and register descriptions for the
System module, see the Device Configurations section and the Documentation Support section of this
document for the ARM Subsystem Guide.
DM6446 has several means of managing power consumption. There is extensive use of clock gating,
which reduces the power used by global device clocks and individual peripheral clocks. The DSP and
VICP power can be disabled through register settings. Voltage/Frequency scaling can be used to allow the
user to lower the core power supply voltage if the frequency needs for a particular application are lower.
Clock management can be utilized to reduce clock frequencies in order to reduce switching power. For
more details on power management techniques, see the Device Configurations and Peripheral sections of
this document and the Documentation Support section of this document for the ARM Subsystem Guide.
DM6446 gives the programmer full flexibility to use any and all of the previously mentioned capabilities to
customize an optimal power management strategy. Several typical power management scenarios are
described in the following sections.
2.3.14.1
Standby Power Mode
This mode consumes the lowest power, with the minimum set of modules kept alive that are required to
wake up the chip to a higher power mode. DSP and coprocessor subsystems are not powered. The rest of
the chip is powered and clocks are suspended, except for GPIO (interrupts), UARTs, I2C (in slave mode),
and the PWM peripheral. PLLs are operating in bypass mode. 27-MHz clock is the only clock available to
the system. DDR2 clock is suspended and the DDR2 Memory Controller is put into self-refresh mode.
2.3.14.2
Low-Power Mode
This mode is for the ARM to sustain some basic control functions. DSP and coprocessor subsystems are
not powered. The rest of the chip is powered, but most clocks are suspended, except for ARM, GPIO,
UARTs, SPI, I2C, PWMs, and Timers. PLLs are operating in bypass mode. 27-MHz clock is the only clock
available to the system. ARM runs at 13.5 MHz, and handles all peripherals by direct access. DDR2 clock
is suspended and DDR2 Memory Controller is put into self-refresh mode. ARM will not have access to
DDR2 and its caches are either frozen or inaccessible.
2.3.14.3
Active Power Mode
The entire chip is powered. All modules operate at nominal clock frequency. Unused peripherals have
their clocks suspended. Active peripherals have their clocks suspended when unneeded.
Device Overview
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