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參數(shù)資料
| 型號(hào)： | TMX320DM6446ZWT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media System on-Chip |
| 中文描述： | 數(shù)字媒體系統(tǒng)芯片 |
| 文件頁(yè)數(shù)： | 31/214頁(yè) |
| 文件大小： | 1699K |
| 代理商： | TMX320DM6446ZWT |
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P
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
Table 2-13. EMIFA Terminal Functions
SIGNAL
NAME
IPD/
IPU
(2)
TYPE
(1)
DESCRIPTION
NO.
EMIFA BOOT CONFIGURATION
This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is
sampled to set the EMIFA data bus width (EM_WIDTH). For an 8-bit wide EMIFA
data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data bus, EM_WIDTH = 1.
After reset, it is video encoder output COUT2 or RGB666/888 Blue output data bit
5 B5.
This pin is multiplexed between DSP boot and the VPBE. At reset, the input state
is sampled to set the DSP boot source DSP_BT. The DSP is booted by the ARM
when DSP_BT=0. The DSP boots from EMIFA when DSP_BT=1.
After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit 6
output B6.
COUT2/
B5/
EM_WIDTH
A17
I/O/Z
IPD
COUT3/
B6/
DSP_BT
B17
I/O/Z
IPD
YOUT0/
G5/
AEAW0
YOUT1/
G6/
AEAW1
YOUT2/
G7/
AEAW2
YOUT3/
R3/
AEAW3
YOUT4/
R4/
AEAW4
D15
I/O/Z
IPD
D16
I/O/Z
IPD
These pins are multiplexed between EMIFA and the VPBE. At reset, the input
states of AEAW[4:0] are sampled to set the EMIFA address bus width. See the
Peripheral Selection at Device Reset section for details.
After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and
Green data bit outputs G5, G6, G7, R3, and R4.
D17
I/O/Z
IPD
D18
I/O/Z
IPD
E15
I/O/Z
IPD
EMIFA FUNCTIONAL PINS: ASYNC / NOR
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous
IPD
memories (i.e., NOR flash) or NAND flash. This is the chip select for the default
boot and ROM boot modes.
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous
IPD
memories (i.e., NOR flash) or NAND flash.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip
Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or
IPD
NAND flash.
For GPIO, it is GPIO9.
For VLYNQ, it is the Serial Clock run request VLYNQ_SCRUN.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip
Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or
IPD
NAND flash.
For GPIO, it is GPIO pin 8 GPIO8
For VLYNQ, it is the clock VLYNQ_CLOCK.
This pin is multiplexed between EMIFA and ATA/CF. For EMIFA, it is read/write
IPD
output EM_R/W.
For ATA/CF, it is interrupt request input INTRQ.
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF. For
EMIFA, it is wait state extension input EM_WAIT.
IPD
For NAND/SmartMedia/xD, it is ready/busy input (RDY/BSY).
For ATA/CF, it is IO Ready input IORDY.
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF. For
EMIFA, it is output enable output EM_OE.
IPD
For NAND/SmartMedia/xD, it is read enable output (RE).
For CF, it is read strobe output (IORD).
For ATA, it is read strobe output DIOR.
EM_CS2
C2
I/O/Z
EM_CS3
B1
I/O/Z
EM_CS4/
GPIO9/
VLYNQ_SCRUN
T2
I/O/Z
EM_CS5/
GPIO8/
VLYNQ_CLOCK
T1
I/O/Z
EM_R/W/
INTRQ
G3
I/O/Z
EM_WAIT/
(RDY/BSY)/
IORDY
F1
I/O/Z
EM_OE/
(RE)/
(IORD)/
DIOR
H4
I/O/Z
(1)
(2)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k
resistor should be used.)
Device Overview
31
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| TMX320DM6467TZUT1 | 制造商:Texas Instruments 功能描述: |
| TMX320DM6467ZUT | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Dig Media System-on- Chip RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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| TMX320DM648ACUT7 | 制造商:Texas Instruments 功能描述:- Trays |
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