
Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
577
Agere Systems Inc.
23 Digital Jitter Attenuation Controller Functional Description
Table of Contents
Contents
Page
23 Digital Jitter Attenuation Controller Functional Description .............................................................................577
23.1 Introduction...............................................................................................................................................578
23.2 Features...................................................................................................................................................578
23.3 Functional Block Diagram of the DJA Block.............................................................................................579
23.4 Digital Jitter Attenuation Controller Operation..........................................................................................579
23.4.1 PLL Bandwidth and Damping Factor Control ................................................................................ 580
23.4.2 PLL Order Control ......................................................................................................................... 580
23.4.3 DS1/E1 Clock Edge Control .......................................................................................................... 580
Figures
Page
Figure 99. DJA Block with I/O Connections to Other Blocks in the Device ...........................................................578
Figure 100. Basic Functional Flow of the DJA Block.............................................................................................579
Tables
Page
Table 634. PLL Bandwidth Control Parameters.....................................................................................................580
Table 635. First-Order Mode Duration Control ......................................................................................................580