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SCSI Operating Registers
SYM53C825A/825AE Data Manual
5-11
Bits 2-0 CCF2-0 (Clock Conversion Factor)
T hese bits select a factor by which the fre-
quency of SCLK is divided before being pre-
sented to the SCSI core. T he synchronous
portion of the SCSI core can be run at a differ-
ent clock rate for fast SCSI, using the Synchro-
nous Clock Conversion Factor bits. T he bit
encoding is displayed in the table below. All
other combinations are reserved and should
never be used.
Note: It is important that these bits be set to the
proper values to guarantee that the
SYM53C825A meets the SCSI timings as
defined by the ANSI specification.
Note: For additional information on how the
synchronous transfer rate is determined,
refer to Chapter 2, “Functional
Description.”
Register 04 (84)
SCSI Chip ID (SCID)
Read/Write
Bit 7
Reserved
Bit 6
RRE (E nable Response to
Reselection)
When this bit is set, the SYM53C825A is
enabled to respond to bus-initiated reselection
at the chip ID in the RESPID0 and RESPID1
registers. Note that the SYM53C825A will not
automatically reconfigure itself to initiator
mode as a result of being reselected.
Bit 5
SRE (E nable Response to Selection)
When this bit is set, the SYM53C825A is able
to respond to bus-initiated selection at the chip
ID in the RESPID0 and RESPID1 registers.
Note that the SYM53C825A will not automat-
ically reconfigure itself to target mode as a
result of being selected.
Bit 4
Reserved
Bits 3-0 E ncoded Chip SCSI ID, bits 3-0
T hese bits are used to store the SYM53C825A
encoded SCSI ID. T his is the ID which the
chip will assert when arbitrating for the SCSI
bus. T he IDs that the SYM53C825A will
respond to when being selected or reselected
are configured in the RESPID0 and RESPID1
registers. T he priority of the 16 possible IDs, in
descending order is:
SCF2
CCF2
SCF1
CCF1
SCF0
CCF0
Factor
Frequency
SCSI Clock
(MHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SCLK /3
SCLK /1
SCLK /1.5
SCLK /2
SCLK /3
Reserved
Reserved
Reserved
50.01-75
16.67-25
25.01-37.5
37.51-50
50.01-75
RES
7
RRE
6
SRE
5
RES
4
ENC3
3
ENC2
2
ENC1
1
ENC0
0
Default>>>
X
0
0
X
0
0
0
0
Highest
4
Lowest
12
7
6
5
3
2
1
0
15
14
13
11
10
9
8