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參數(shù)資料
| 型號(hào)： | SYM53C825AE |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 57/225頁(yè) |
| 文件大小： | 1237K |
| 代理商： | SYM53C825AE |
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PCI Functional Description
Configuration Registers
SYM53C825A/53C825AE Data Manual
3-13
Register 30h
Expansion ROM Base Address
Read/Write
T his four-byte register handles the base address
and size information for expansion ROM. It func-
tions exactly like the Base Address Zero and Base
Address One registers, except that the encoding of
the bits is different. T he upper 21 bits correspond
to the upper 21 bits of the expansion ROM base
address.
T he Expansion ROM Enable bit, bit 0, is the only
bit defined in this register. T his bit is used to con-
trol whether or not the device accepts accesses to
its expansion ROM. When the bit is set, address
decoding is enabled, and a device can be used with
or without an expansion ROM depending on the
system configuration. To access the external mem-
ory interface, the Memory Space bit in the Com-
mand register must also be set.
T he host system detects the size of the external
memory by first writing the Expansion ROM Base
Address register with all ones and then reading
back the register. T he SYM53C825A will respond
with zeros in all don’t care locations. T he ones in
the remaining bits represent the binary version of
the external memory size. For example, to indicate
an external memory size of 32 K B, this register,
when written with ones and read back, will return
ones in the upper 17 bits.
Register 34h
Capability Pointer
Read Only
T his register provides an offset into the function’s
PCI Configuration Space for the location of the
first item in the capabilities linked list. Only the
SYM53C825AE sets this register to 40h. T he
capability pointer replaces the General Purpose
Pin Control Register in earlier revisions of the
SYM53C825A.
Register 3Ch
Interrupt Line
Read/Write
T his register is used to communicate interrupt line
routing information. POST software will write the
routing information into this register as it initiates
and configures the system. T he value in this regis-
ter tells which input of the system interrupt con-
troller(s) the device’s interrupt pin has been
connected to. Values in this register are specified by
system architecture.
Register 3Dh
Interrupt Pin
Read Only
T his register tells which interrupt pin the device
uses. Its value is set to 01h, for the INTA/ signal.
Register 3Eh
Min_Gnt
Read Only
Register 3Fh
Max_Lat
Read Only
T hese registers are used to specify the desired set-
tings for Latency T imer values. Min_Gnt is used to
specify how long a burst period the device needs.
Max_Lat is used to specify how often the device
needs to gain access to the PCI bus. T he value
specified in these registers is in units of 0.25
microseconds. Values of zero indicate that the
device has no major requirements for the settings
of Latency T imers. T he SYM53C825A sets the
Min_Gnt register to 11h and the Max_Lat register
to 40h.
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